CC256X Datasheet, PDF (21/51 Pages) Texas Instruments – Bluetooth® Smart Ready Controller

CC256x
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SWRS121C – JULY 2012 – REVISED OCTOBER 2013
3.5.3.4 Frame Idle Period
The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of
the frame, after all data are transferred.
The CC256x device supports frame idle periods both as master and slave of the codec bus.
When the CC256x device is the master of the interface, the frame idle period is configurable. There are
two configurable parameters:
• Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of
the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.
• Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time
is given in multiples of clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.
Between both frame-sync signals there are 70 clock cycles (instead of 100). The clock idle period starts
60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. This means that the
idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end
before the beginning of the idle period.
Figure 3-13 shows the frame idle timing.
Frame_Sync
Frame period
Data_In
Data_Out
Clock
Frame idle
Clk_Idle_Start
Clk_Idle_End
Figure 3-13. Frame Idle Period
frmidle_swrs064
3.5.3.5 Clock-Edge Operation
The codec interface of the CC256x device can work on the rising or the falling edge of the clock and can
sample the frame-sync signal and the data at inversed polarity.
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