BQ24740_14 Datasheet, PDF (21/33 Pages) Texas Instruments – Host-Controlled Multi-Chemistry Battery Charger

bq24740
www.ti.com............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009
250 V
R_ISYNSET
=
I_SYN x R_SENSE
W
(6)
RSENSE
I_SYN
SRN
SRP
3.3 V
20X
I =1V/R_ISYNSET
1V
SYNCH
UCP
5 kΩ
ISYNSET
R _ ISYNSET
Figure 29. Charge Undercurrent Comparator, ISYNSET Comparator Block
HIGH ACCURACY IADAPT USING CURRENT SENSE AMPLIFIER (CSA)
An industry standard, high accuracy current sense amplifier (CSA) is used to monitor the input current by the
host or some discrete logic through the analog voltage output of the IADAPT pin. The CSA amplifies the input
sensed voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times
the input differential voltage. Once PVCC is above 5 V and ACDET is above 0.6V, IADAPT no longer stays at
ground, but becomes active. If the user wants to lower the voltage, they could use a resistor divider from IOUT to
AGND, and still achieve accuracy over temperature as the resistors can be matched their thermal coefficients.
A 100-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, after the 100-pF capacitor, if additional filtering is desired. Note that adding filtering also
adds additional response delay.
INPUT OVERVOLTAGE PROTECTION (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. The controller enters ACOV
when ACDET > 3.1 V and charge is disabled. ACOV is not latched—normal operation resumes when the ACDET
voltage returns below 3.1 V. ACOV threshold is 130% of the adapter-detect threshold.
INPUT UNDERVOLTAGE LOCK OUT (UVLO)
The system must have a minimum 4 V PVCC voltage to allow proper operation. This PVCC voltage could come
from either input adapter or battery, using a diode-OR input. When the PVCC voltage is below 4 V the bias
circuits REGN and VREF stay inactive, even with ACDET above 0.6 V.
INPUT CURRENT LOW-POWER MODE DETECTION
To optimize the system performance, the HOST monitors the adapter current. Once the adapter current is above
threshold set via LPREF, LPMD pin sends signal to HOST. The signal alarms the host that input power has
exceeded the programmed limit, allowing the host to throttle back system power by reducing clock frequency,
lowering rail voltages, or disabling certain parts of the system. The LPMD pin is an open-drain output. Connect a
pull-up resistor to LPMD. The output is logic HI when the IADAPT output voltage (I_ADAPT = 20 × V_ACP-ACN) is lower
than the LPREF input voltage. The LPREF threshold is set by an external resistor divider using VREF. A
hysteresis can be programmed by a positive feedback resistor from LPMD pin to the LPREF pin.
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