TMS320DM647_16 Datasheet, PDF (20/190 Pages) Texas Instruments – Digital Media Processor

TMS320DM647
TMS320DM648
SPRS372H – MAY 2007 – REVISED APRIL 2012
www.ti.com
2.6 Terminal Functions
The terminal functions tables (Table 2-4 through Table 2-5) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see Section 3.
All device boot and configuration pins are multiplexed with functional pins. These pins function as device
boot and configuration pins only during device reset. When both the reset pin (RESET) and the power-on
reset pin (POR) are deasserted, the input states of these multiplexed device boot and configuration pins
are sampled and latched into the BOOTCFG register. For proper device operation, these pins must be
pulled up/down to the desired value via an external resistor.
Table 2-4. Terminal Functions
TERMINAL NAME
NO TYPE⁽
1)
INTERNAL
PULLUP/
PULLDOWN
OPER DESCRIPTION
VOLT
Clock/PLL Configuration
CLKIN1
M1
I
IPD
3.3 V Clock Input for PLL1
CLKIN2
F1
I
IPD
3.3 V Clock Input for PLL2
REFCLKN ⁽²⁾
AC11 I
Differential Reference Clock input (negative) for SGMII
REFCLKP ⁽²⁾
AB11 I
Differential Reference Clock input (positive) for SGMII
PLLV1
N3
A
1.8 V 1.8-V I/O Supply Voltage for PLL1
PLLV2
G7
A
1.8 V 1.8-V I/O Supply Voltage for PLL2
SYSCLK5
M3 I/O/Z
IPD
3.3 V Clock out of device speed/4
JTAG
TCLK
H23
I
IPU
3.3 V JTAG Test Port Clock
TDI
J22
I
IPU
3.3 V JTAG Test Port Data In
TDO
J23 OZ
IPU
3.3 V JTAG Test Port Data Out
TMS
L22
I
IPU
3.3 V JTAG Test Port Mode Select
TRST
L23
I
IPD
3.3 V JTAG Test Port Reset
EMU0
K23 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 0
EMU1
K22 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 1
EMU2
K21 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 2
EMU3
K20 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 3
EMU4
L18 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 4
EMU5
J21 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 5
EMU6
K19 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 6
EMU7
H21 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 7
EMU8
J20 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 8
EMU9
H20 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 9
EMU10
J19 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 10
EMU11
K18 I/O/Z
IPU
3.3 V JTAG Test Port Emulation 11
RESET/INTERRUPTS
NMI
J18
I
IPD
3.3 V Nonmaskable Interrupt
RESETSTAT
H19 O
3.3 V Reset Status Pin
RESET
G20
I
3.3 V Device Reset
POR
H18
I
3.3 V Power On Reset
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) The clock input buffers on the REFCLKP/N pins are compatible with LVDS and LVPECL clock sources. These input buffers include a
100-Ω termination (P to N) and a common-mode biasing. Because the common-mode biasing is included, the clock source must be AC
coupled.
20
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