TMS320DM647_16 Datasheet, PDF(14/190 Page) Texas Instruments

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TMS320DM647_16 Datasheet, PDF (14/190 Pages) Texas Instruments – Digital Media Processor

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TMS320DM647

TMS320DM648

SPRS372H â MAY 2007 â REVISED APRIL 2012

www.ti.com

START

ADDRESS

0x02CC 0000

0x02D0 0000

0x02D0 2000

0x02D0 3000

0x02D0 4000

0x02D0 4800

0x02D0 4C00

0x02D0 5000

0x02D0 5800

0x02DC 0000

0x02E0 0000

0x02E0 4000

0x0300 0000

0x0400 0000

0x1000 0000

0x2000 0000

0x3000 0000

0x3000 0100

0x3400 0000

0x3400 0100

0x3800 0000

0x3C00 0000

0x3D00 0000

0x3E00 0000

0x4000 0000

0x5000 0000

0x5200 0000

0x5400 0000

0x5600 0000

0x5800 0000

0x5A00 0000

0x5C00 0000

0x5E00 0000

0x6000 0000

0x6200 0000

0x6400 0000

0x6600 0000

0x6800 0000

0x7000 0000

0x7800 0000

0x8000 0000

0x9000 0000

0xA000 0000

0xA400 0000

0xB000 0000

0xB400 0000

0xC000 0000

Table 2-3. Memory Map Summary (continued)

END

ADDRESS

0x02CF FFFF

0x02D0 1FFF

0x02D0 2FFF

0x02D0 3FFF

0x02D0 47FF

0x02D0 4BFF

0x02D0 4FFF

0x02D0 57FF

0x02DB FFFF

0x02DF FFFF

0x02E0 3FFF

0x02FF FFFF

0x03FF FFFF

0x0FFF FFFF

0x1FFF FFFF

0x2FFF FFFF

0x3000 00FF

0x33FF FFFF

0x3400 00FF

0x37FF FFFF

0x3BFF FFFF

0x3CFF FFFF

0x3DFF FFFF

0x3FFF FFFF

0x4FFF FFFF

0x51FF FFFF

0x53FF FFFF

0x55FF FFFF

0x57FF FFFF

0x59FF FFFF

0x5BFF FFFF

0x5DFF FFFF

0x5FFF FFFF

0x61FF FFFF

0x63FF FFFF

0x65FF FFFF

0x67FF FFFF

0x6FFF FFFF

0x77FF FFFF

0x7FFF FFFF

0x8FFF FFFF

0x9FFF FFFF

0xA3FF FFFF

0xAFFF FFFF

0xB3FF FFFF

0xBFFF FFFF

0xCFFF FFFF

SIZE

(Bytes)

256K

746K

256K

16K

2M â 16K

16M

192M

256M

256

64M â 256

256

64M â 256

64M

16M

32M

256M

32M

128M

256M

64M

256 - 64M

64M

256 - 64M

256M

C64x+

MEMORY MAP

Reserved

Ethernet Subsystem CPPI RAM(1)

Ethernet Subsystem Control

Ethernet Subsystem 3PSW

Ethernet Subsystem MDIO

Ethernet Subsystem SGMII0

Ethernet Subsystem SGMII1 (DM648 only)

Reserved

VLYNQ

Reserved

PCI Data

VP0 ChannelA Data

VP0 ChannelB Data

VP1 ChannelA Data

VP1 ChannelB Data

VP2 ChannelA Data

VP2 ChannelB Data

Reserved

VP3 ChannelA Data

VP3 ChannelB Data

VP4 ChannelA Data

VP4 ChannelB Data

Reserved

EMIFA Configuration

DDR2 EMIF Configuration

Reserved

EMIFA CE2(2)

Reserved

EMIFA CE3(2)

Reserved

(1) The 8K CPPI Descriptor memory is mapped to an address range 0x02C8 2000 - 0x02C8 3FFF, from the perspective of the Ethernet

subsystem 3PSW. The buffer descriptors, when accessed from the C64x+, are addressed from 0x02D0 0000. However, within these

buffer descriptors, when the pointer to the next buffer descriptor is programmed, the Ethernet subsystem 3PSW is interpreting this value.

Thus, this programmed value should be in the address range starting from 0x02C8 2000.

(2) The EMIFA CS0 and CS1 are not functionally supported; therefore, they are not pinned out.

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