ADS6149_14 Datasheet, PDF (20/71 Pages) Texas Instruments – 14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs

ADS6149/ADS6129
ADS6148/ADS6128
SLWS211B – JULY 2008 – REVISED OCTOBER 2008 ..................................................................................................................................................... www.ti.com
DESCRIPTION OF SERIAL REGISTERS
A)
A7–A0 IN HEX
D7
00
<RESET>
Software Reset
D6
D5
D4
D3
D2
D1
D0
<SERIA
0
0
0
0
0
0
L
READO
UT>
D7
<RESET>
1
Software reset applied – resets all internal registers and self-clears to 0.
D0
<SERIAL READOUT>
0
Serial readout disabled
1
Serial readout enabled, Pin OVR_SDOUT functions as serial data readout.
A)
A7–A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
<ENABLE
20
0
0
0
0
0
LOW SPEED
0
0
MODE>
D2
<ENABLE LOW SPEED MODE>
0
LOW SPEED mode disabled. Use for sampling frequency > 100 MSPS
1
Enable LOW SPEED mode for sampling frequencies ≤ 100 MSPS.
B)
A7–A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
3F
0
<REF>
0
0
<PDN
GLOBAL>
<STANDBY>
<PDN
OBUF>
D0
<PDN OBUF> Power down output buffer
0
Output buffer enabled
1
Output buffer powered down
D1
<STANDBY>
0
Normal operation
1
ADC alone powered down. Internal references, output buffers are active. Quick wake-up time
D2
0
1
D6,D5
00
01
11
<PDN GLOBAL>
Normal operation
Total power down – ADC, internal references and output buffers are powered down. Slow wake-up time.
<REF> Internal or external reference selection
MODE pin controls reference selection
Internal reference enabled
External reference enabled
C)
A7–A0 IN HEX
41
D7
D6
<LVDS CMOS>
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
D7,D6
00
10
11
<LVDS CMOS>
DFS pin controls LVDS or CMOS interface selection
DDR LVDS interface
Parallel CMOS interface
20
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