LMK00304_16 Datasheet, PDF (2/39 Pages) Texas Instruments – 3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00304
SNAS577F – FEBRUARY 2012 – REVISED MARCH 2016
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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Functional Block Diagram .................................... 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions ...................... 6
7.4 Thermal Information .................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Typical Characteristics ............................................ 14
8 Parameter Measurement Information ................ 18
8.1 Differential Voltage Measurement Terminology...... 18
9 Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 20
10 Application and Implementation........................ 22
10.1 Driving the Clock Inputs ........................................ 22
10.2 Crystal Interface .................................................... 23
10.3 Termination and Use of Clock Drivers .................. 24
11 Power Supply Recommendations ..................... 29
11.1 Power Supply Sequencing .................................... 29
11.2 Current Consumption and Power Dissipation
Calculations.............................................................. 29
11.3 Power Supply Bypassing ...................................... 30
11.4 Thermal Management ........................................... 31
12 Device and Documentation Support ................. 33
12.1 Documentation Support ........................................ 33
12.2 Community Resources.......................................... 33
12.3 Trademarks ........................................................... 33
12.4 Electrostatic Discharge Caution ............................ 33
12.5 Glossary ................................................................ 33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 33
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (May 2013) to Revision F
Page
• Added "Ultra-Low Additive Jitter" to document title ................................................................................................................ 1
• Added, updated, or renamed the following sections: Specifications; Detailed Description; Application and
Implementation; Power Supply Recommendations; Device and Documentation Support; Mechanical, Packaging,
and Ordering Information ....................................................................................................................................................... 1
• Changed Cin (typ) from 1 pF to 4 pF (based on updated test method) in Electrical Characteristics: Crystal Interface ....... 8
• Added footnote for V_{I_SE} parameter in the Electrical Characteristics table. .......................................................................... 8
• Added "Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz
Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVPECL Outputs ....................... 9
• Added "Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz” parameter with 100 MHz and 156.25 MHz
Test conditions, Typical values, Max values, and footnotes in Electrical Characteristics: LVDS Outputs .......................... 10
• Added new paragraph at end of Driving the Clock Inputs ................................................................................................... 22
• Changed "LMK00301" to "LMK00304" in Figure 27 and Figure 28 .................................................................................... 23
• Changed Cin = 4 pF (typ, based on updated test method) in Crystal Interface................................................................... 23
• Added POWER SUPPLY SEQUENCING ........................................................................................................................... 29
Changes from Revision D (February 2013) to Revision E
Page
• Changed V_CM text to condition for V_IH to V_CM parameter group. ............................................................................................ 8
• Deleted V_IH min value from Electrical Characteristics table. .................................................................................................. 8
• Deleted V_IL max value from Electrical Characteristics table................................................................................................... 8
• Added V_{I_SE} parameter and spec limits with corresponding table note to Electrical Characteristics Table. .......................... 8
• Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Revised to better
correspond with information in Electrical Characteristics Table. .......................................................................................... 22
• Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section. .............. 22
• Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic............... 23
• Added text to second paragraph of Termination for AC Coupled Differential Operation to explain graphic update to
2
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