LMK00304_16 Datasheet, PDF (12/39 Pages) Texas Instruments – 3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

LMK00304
SNAS577F – FEBRUARY 2012 – REVISED MARCH 2016
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Electrical Characteristics (continued)
Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ± 5%, -40 °C ≤ T_A ≤ 85 °C, CLKin driven
differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A
= 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. ^{(1) (2)}
TEST CONDITIONS
MIN
TYP
MAX UNIT
LVCMOS OUTPUT (REFout)
f_CLKout
Output Frequency
Range ⁽⁵⁾
C_L ≤ 5 pF
DC
250 MHz
Jitter_ADD
Additive RMS Jitter
Integration Bandwidth
1 MHz to 20 MHz⁽¹¹⁾
Vcco = 3.3 V, C_L ≤ 5 pF
100 MHz, Input Slew
rate ≥ 3 V/ns
95
fs
Noise Floor
DUTY
Noise Floor
f_OFFSET ≥ 10 MHz^{(14) (15)}
Duty Cycle⁽⁵⁾
Vcco = 3.3 V, C_L ≤ 5 pF
100 MHz, Input Slew
rate ≥ 3 V/ns
50% input clock duty cycle
45%
-159.3
dBc/Hz
55%
V_OH
Output High Voltage
1 mA load
V_OL
Output Low Voltage
I_OH
Output High Current
(Source)
Vcco = 3.3 V
Vcco = 2.5 V
Vo = Vcco / 2
I_OL
Output Low Current
(Sink)
Vcco = 3.3 V
Vcco = 2.5 V
Vcco -
0.1
V
0.1 V
28
mA
20
28
mA
20
t_R
Output Rise Time
20% to 80%^(7)(16)
250 MHz, Uniform transmission line up to 10
t_F
Output Fall Time
80% to 20%^(7)(16)
inches with 50-Ω characteristic impedance, R_L = 50
Ω to GND, C_L ≤ 5 pF
t_EN
t_DIS
Output Enable Time⁽¹⁷⁾
Output Disable Time^{(17) CL ≤ 5 pF}
225
400 ps
225
400 ps
3 cycles
3 cycles
(17) Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly,
Output Disable Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The
REFout_EN signal should have an edge transition much faster than that of the input clock period for accurate measurement.
12
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