LM3S6918 Datasheet, PDF (192/689 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

System Control
Bit/Field
21:14
13
12
11
10
Name
reserved
PWRDN
reserved
BYPASS
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
1
1
1
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
See Table 5-5 on page 177 for programming guidelines.
Note:
The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
192
June 19, 2012
Texas Instruments-Production Data