LMK03200_14 Datasheet, PDF (19/50 Pages) Texas Instruments – Family Precision 0-Delay Clock Conditioner with Integrated VCO

LMK03200
www.ti.com
SNAS478B – JULY 2009 – REVISED AUGUST 2009
Recommended Programing Sequence, with 0-Delay Mode
The lock procedure when using the 0-delay mode has two steps. The first is to complete the frequency
calibration routine for the target frequency while not in 0-delay mode. The second step is to activate 0-delay
mode and re-program the PLL_N divider to accommodate the additional divide in the clock output path so that
phase lock can be achieved with the reference input clock.
Global_CLK_EN and each output being used should be enabled in step 1. If the user desires for no output from
the clock outputs during frequency lock, the GOE pin should be held low.
Step 1
• GOE pin is held low to keep outputs from toggling. Disabling the clock output with MICROWIRE should not be
used so that when more than one clock output is used, they will all be synchronized together when using
0_DELAY_MODE. Otherwise a separate SYNC* is required ensure all outputs are synchronized together
after all steps are completed.
• Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset
bit is set in R0, the other R0 bits are ignored.
– If R0 is programmed again, the reset bit is programmed clear (RESET = 0).
• Program R0 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings.
Outputs being used should be enabled.
– R0: DLD_MODE2 = 1 (Digital Lock Detect is now Frequency Calibration Routine Complete)
– R0: 0_DELAY_MODE = 0
– R0: FB_MUX = desired feedback path for 0-delay mode.
– RX: CLKoutX_EN = 1 for used clock outputs.
• Program R8 for optimum phase noise performance.
• Program R9 with Vboost setting if necessary.
• Program R11 with DIV4 setting if necessary.
• Program R13 with oscillator input frequency and internal loop filter values.
• Program R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, PLL_R
divider, and global PLL R delay.
– R14: EN_CLKout_Global = 1
– R14: PLL_MUX = 3 or 4 for frequency calibration routine complete signal.
• Program R15 with PLL charge pump gain, VCO divider, PLL N divider, and global PLL N delay. The
frequency calibration routine starts.
Now the LD pin should be monitored for the frequency calibration routine completed signal to be asserted if
PLL_MUX was set to 3 or 4 and DLD_MODE2 = 1. Otherwise wait 2 ms for the frequency calibration routine to
complete. Once the frequency calibration routine is completed step 2 may be executed to achieve 0-delay mode.
With the addition of the clock output divide in the feedback path, the total N feedback divide will change and the
device will need to be programmed in this step to accommodate this extra divide.
Step 2
• Program R0 with the same settings as in step 1 except:
– 0_DELAY_MODE = 1 to activate 0-delay mode.
• The output being used for feedback must be enabled for the device to lock. This means that...
– GOE pin is high. (set high if low from step 1).
– SYNC* pin is high.
– CLKoutX_EN bit is 1. (For all clocks being used)
– EN_CLKout_Global bit is 1.
• Special feedback cases:
– When CLKout 5 is used for feedback, CLKout 6 must also be enabled (CLKout6_EN = 1). The
configuration of the channel does not matter.
– When FBCLKin/FBCLKin* is used for feedback, CLKout 5 and CLKout 6 must be enabled (CLKout5_EN =
1 and CLKout6_EN = 1). The configuration of the channels does not matter, except when CLKout 5 or
CLKout 6 is the source channel which drives FBCLKin/FBCLKin*.
• Program R15 with new PLL_N value.
Copyright © 2009, Texas Instruments Incorporated
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