LM3424 Datasheet, PDF (19/69 Pages) National Semiconductor (TI) – Constant Current N-Channel Controller with Thermal Foldback for Driving LEDs

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LM3424, LM3424-Q1
SNVS603C – AUGUST 2009 – REVISED AUGUST 2015
Feature Description (continued)
Figure 24 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output
pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The
RHP zero adds 20dB/decade of gain while loosing 45°/decade of phase which places the crossover frequency
(when the gain is zero dB) extremely high because the gain only starts falling again due to the high frequency
pole (not modeled or shown in figure). The phase will be below -180° at the crossover frequency which means
there is no phase margin (180° + phase at crossover frequency) causing system instability. Even if the output
pole is below the RHP zero, the phase will still reach -180° before the crossover frequency in most cases yielding
instability.
I_LED
V_SNS R_SNS
C_FS
R_HSP
R_HSN
R_FS
sets ö_P3 R_CSH
sets ö_P2
C_CMP
LM3424
High-Side
HSP ^{Sense Amplifier}
HSN
Thermal Foldback Current
CSH
COMP
1.24V
Error Amplifier
To PWM
R_O
Comparator
Figure 25. Compensation Circuitry
To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the
crossover frequency. A simple compensator using a single capacitor at the COMP pin (C_CMP) will add a dominant
pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as
shown in Figure 24), the RHP zero places extreme limits on the achievable bandwidth with this type of
compensation. However, because an LED driver is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.
The dominant compensation pole (ω_P2) is determined by C_CMP and the output resistance (R_O) of the error
amplifier (typically 5 MΩ):
1
ω_P2= _{5 x 106Ω x CCMP}
(18)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across R_SNS to filter the
ESL of the sense resistor at the same time. Figure 25 shows how the compensation is physically implemented in
the system.
The high frequency pole (ω_P3) can be calculated:
Z_P3
=
R_FS
1
x
C_FS
(19)
The total system transfer function becomes:
¨¨©§^1- _Z^s_Z1¸¸¹·
T = T_U0 x _{¨¨©§1+ ZsP1¸¸¹· x ¨¨©§1+ ZsP2¸¸¹· x ¨¨©§1+ ZsP3¸¸¹·}
(20)
The resulting compensated loop gain frequency response shown in Figure 26 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:
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