LMH1981 Datasheet, PDF (18/24 Pages) National Semiconductor (TI) – Multi-Format Video Sync Separator

LMH1981
SNLS214H – APRIL 2006 – REVISED MARCH 2013
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For example, a significant decrease in APL such as a white-to-black field transition will cause a positive-going
shift in the sync tips characterized by the source’s RC time constant, t_RC-OUT (150Ω*C_OUT). The LMH1981’s input
clamp circuitry may have difficulty stabilizing the input signal under this type of shifting; consequently, the
unstable signal at V_IN may cause missing sync output pulses to result, unless a proper value for C_IN is chosen.
To avoid this potential problem when interfacing AC-coupled sources to the LMH1981, it’s necessary to introduce
a voltage droop component via C_IN to compensate for video signal shifting related to changes in the APL. This
can be accomplished by selecting C_IN such that the effective time constant of the LMH1981’s input circuit, t_RC-IN,
is less than t_RC-OUT.
The effective time constant of the input circuit can be approximated as: t_RC-IN = (R_S+R_I)*C_IN*T_LINE/T_CLAMP, where
R_S = 150Ω, R_I = 4000Ω (input resistance), T_LINE ∼ 64 μs for NTSC, and T_CLAMP = 250 ns (internal clamp
duration). A white-to-black field transition in NTSC video through C_OUT will exhibit the maximum sync tip shifting
due to its long line period (T_LINE). By setting t_RC-IN < t_RC-OUT, the maximum value of C_IN can be calculated to
ensure proper operation under this worst-case condition.
For instance, t_RC-OUT is about 33 ms for C_OUT = 220 µF. To ensure t_RC-IN < 33 ms, C_IN must be less than 31 nF.
By choosing C_IN = 0.01 μF, the LMH1981 will function properly with AC-coupled video sources using C_OUT ≥ 220
μF.
PCB LAYOUT CONSIDERATIONS
LMH1981 IC Placement
The LMH1981 should be placed such that critical signal paths are short and direct to minimize PCB parasitics
from degrading the high-speed video input and logic output signals.
Ground Plane
A two-layer, FR-4 PCB is sufficient for this device. One of the PCB layers should be dedicated to a single, solid
ground plane that runs underneath the device and connects the device GND pins together. The ground plane
should be used to connect other components and serve as the common ground reference. It also helps to reduce
trace inductances and minimize ground loops. Try to route supply and signal traces on another layer to maintain
as much ground plane continuity as possible.
Power Supply Pins
The power supply pins should be connected together using short traces with minimal inductance. When routing
the supply traces, be careful not to disrupt the solid ground plane.
For high frequency bypassing, place 0.1 µF SMD ceramic bypass capacitors with very short connections to
power supply and GND pins. Two or three ceramic bypass capacitors can be used depending on how the supply
pins are connected together. Place a 4.7 µF SMD tantalum bypass capacitor nearby all three power supply pins
for low frequency supply bypassing.
R_EXT Resistor
The R_EXT resistor should be a 10 kΩ 1% SMD precision resistor. Place R_EXT as close as possible to the device
and connect to pin 1 and the ground plane using the shortest possible connections. All input and output signals
must be kept away from this pin to prevent unwanted signals from coupling into this pin.
Video Input
The input signal path should be routed using short, direct traces between video source and input pin. Use a 75Ω
input termination and a SMD capacitor for AC coupling the video input to pin 4.
Output Routing
The output signal paths should be routed using short, direct traces to minimize parasitic effects that may degrade
these high-speed logic signals. All output signals should have a resistive load of about 10 kΩ and capacitive load
of less than 10 pF, including parasitic capacitances for optimal signal quality. This is especially important for the
horizontal sync output, in which it is critical to minimize timing jitter. Each output can be protected by current
limiting with a small series resistor, like 100Ω.
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