LMH1981 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – Multi-Format Video Sync Separator

LMH1981
SNLS214H – APRIL 2006 – REVISED MARCH 2013
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LOGIC OUTPUTS
In the absence of a video input signal, the LMH1981 outputs are logic high except for the odd/even field and
video format outputs, which are both undefined, and the composite sync output.
Composite Sync Output
CSOUT (pin 12) simply reproduces the video input sync pulses below the video blanking level. This is obtained
by clamping the video signal sync tip to the internal clamp voltage at V_IN and extracting the resultant composite
sync signal, or CSync. For both bi-level and tri-level syncs, CSync's negative-going leading edge is derived from
the input's negative-going leading edge with a propagation delay.
Horizontal Sync Output
HSOUT (pin 7) produces a negative-polarity horizontal sync signal, or HSync, with very low jitter on its negative-
going leading edge (reference edge) using precise 50% sync slicing. For bi-level and tri-level sync signals, the
horizontal sync leading edge is triggered from the input's sync reference, O_H, with a propagation delay.
HSync was optimized for excellent jitter performance on its leading edge because most video systems are
negative-edge triggered. When HSync is used in a positive-edge triggered system, like an FPGA PLL input, it
must be inverted beforehand to produce positive-going leading edges. The trailing edge of HSync should never
be used as the reference or triggered edge. This is because the trailing edges of HSync are reconstructed for the
broad serration pulses during the vertical interval.
HSync's typical peak-to-peak jitter can be measured using the input-referred jitter test methodology on a real-
time digital oscilloscope by triggering at or near the input's O_H reference and monitoring HSync's leading edge
with 4-sec. variable persistence. This is one way to measure HSync's typical peak-to-peak jitter in the time
domain. Figure 13 and Figure 14 show oscilloscope screenshots demonstrating very low jitter on HSync's leading
edge for 1080I tri-level sync and PAL Black Burst inputs, respectively, from a Tek TG700-AWVG7/AVG7 video
generator with DC-coupled outputs and with LMH1981 V_CC = 3.3V.
Figure 13. Typical HSync Jitter for 1080I Input
Upper: Horizontal Sync Leading Edge (Reference)
Lower: Zoomed In — 400 ps/DIV, 25 mV/DIV
Figure 14. Typical HSync Jitter for PAL Input
Upper: Horizontal Sync Leading Edge (Reference)
Lower: Zoomed In — 1000 ps/DIV, 25 mV/DIV
Vertical Sync Output
VSOUT (pin 8) produces a negative-polarity vertical sync signal, or VSync. VSync's negative-going leading edge
is derived from the 50% point of the first vertical serration pulse with a propagation delay, and its output pulse
width, T_VSOUT, spans approximately three horizontal periods (3H).
Burst/Back Porch Timing Output
BPOUT (pin 13) provides a negative-polarity burst/back porch signal, which is pulsed low for a fixed width during
the back porch interval following the input's sync pulse. The burst/back porch timing pulse is useful as a burst
gate signal for NTSC/PAL color burst synchronization and as a clamp signal for black level clamping (DC
restoration) and sync stripping applications.
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