DS90UR907Q Datasheet, PDF (18/27 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter

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FIGURE 19. BIST Mode Flow Diagram
BER Calculations
It is possible to calculate the approximate Bit Error Rate
(BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24
times the RxCLKIN rate times the test duration. If we assume
a 65MHz RxCLKIN, a 10 minute (600 second) test, and a
PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The
LOCK pin also provides a link status. It the recovery of the C0
and C1 bits does not reconstruct the expected clock signal,
the LOCK pin will switch Low. The combination of the LOCK
and At-Speed BIST PASS pin provides a powerful tool for
system evaluation and performance monitoring.
FIGURE 20. BIST Waveforms
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Optional Serial Bus Control
The DS90UR907Q may be configured by the use of a serial
control bus that is I2C protocol compatible. By default, the I2C
reg_0x00'h is set to 00'h and all configuration is set by control/
strap pins. A write of 01'h to reg_0x00'h will enable/allow con-
figuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since mul-
tiple addresses are supported. See Figure 21.
The serial bus is comprised of three pins. The SCL is a Serial
Bus Clock Input. The SDA is the Serial Bus Data Input / Out-
put signal. Both SCL and SDA signals require an external pull
up resistor to V_DDIO. For most applications a 4.7 k pull up re-
sistor to V_DDIO may be used. The resistor value may be
adjusted for capacitive loading and data rate requirements.
The signals are either pulled High, or driven Low.
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FIGURE 21. Serial Control Bus Connection
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