DS90UR907Q Datasheet, PDF (14/27 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter

Functional Description
The DS90UR907Q converter transmits an FPD-Link interface
(4 LVDS data channels + 1 LVDS clock) with total of 27–bits
of data (24–high speed bits and 3 low speed video control
signals) over a single serial FPD-Link II pair. The serial stream
also contains an embedded clock and the DC-balance infor-
mation which enhances signal quality and supports AC cou-
pling. The device is intended for use with DS90UR908Q or
DS90UR906Q, but is backward compatible with previous
generations of FPD-Link II as well.
The DS90UR907Q can operate in 24-bit color mode(with
VS,HS,DE encoded in the serial stream) or in 18-bit color
mode.
The DS90UR907Q can be configured via external pins or
through the optional serial control bus. It features enhance
signal quality on the link by supporting: selectable VOD level,
selectable de-emphasis signal conditioning and also the
FPD-Link II data coding that provides randomization, scram-
bling, and DC Balanacing of the video data. It also includes
multiple features to reduce EMI associated with display data
transmission. This includes the randomization and scram-
bling of the data and also the system spread spectrum PCLK
support. The DS90UR907Q features power saving with a
powerdown mode, and auto stop clock feature.
See also the Functional Description of the serial control bus
and BIST modes.
The Block Diagram is shown at the beginning of this
datasheet.
DATA TRANSFER
The DS90UR907Q transmits a pixel of data in the following
format: C1 and C0 represent the embedded clock in the serial
stream. C1 is always HIGH and C0 is always LOW. b[23:0]
contain the scrambled RGB data. DCB is the DC-Balanced
control bit. DCB is used to minimize the short and long-term
DC bias on the signal lines. This bit determines if the data is
unmodified or inverted. DCA is used to validate data integrity
in the embedded data stream and can also contain encoded
control (VS,HS,DE). Both DCA and DCB coding schemes are
generated by the DS90UR907Q and decoded by the paring
deserializer automatically. Figure 14 illustrates the serial
stream per PCLK cycle.
Note: The figure only illustrates the bits but does not actually
represent the bit location as the bits are scrambled and bal-
anced continuously.
FIGURE 14. FPD-Link II Serial Stream
30105037
OPERATING MODES AND BACKWARD COMPATIBILITY
(CONFIG[1:0])
The DS90UR907Q is backward compatible with previous
generations of FPD-Link II deserializers. Configuration
modes are provided for backwards compatibility with the
DS90C124 FPD-Link II Generation 1, and also the
DS90UR124 FPD-Link II Generation 2 deserializers by set-
ting the respective mode with the CONFIG[1:0] pins as shown
in Table 1. The selection also determine whether the Video
Control Signal filter feature is enabled or disabled in Normal
mode.
TABLE 1. DS90UR907Q Configuration Modes
CON CON Mode
FIG1 FIG0
Des Device
L
L Normal Mode, Control DS90UR908Q,
Signal Filter disabled DS90UR906Q
L
H Normal Mode, Control DS90UR908Q,
Signal Filter enabled DS90UR906Q
H
L Backwards Compatible DS90UR124,
GEN2
DS99R124
H
H Backwards Compatible DS90C124
GEN1
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Con-
trol Signals (DE, HS, VS) have the following restrictions:
• Normal Mode with Control Signal Filter Enabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are
transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals
with limited transitions. Glitches of a control signal can cause
a visual display error. This feature allows for the chipset to
validate and filter out any high frequency noise on the control
signals. See Figure 15.
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