DS90UR907Q Datasheet, PDF (17/27 Pages) Texas Instruments – 5 - 65 MHz 24-bit Color FPD-Link to FPD-Link II Converter

Stop Clock Feature
The DS90UR907Q will enter a low power SLEEP state when
the RxCLKIN is stopped. A STOP condition is detected when
the input clock frequency is less than 3 MHz. The clock should
be held at a static Low or high state. When the RxCLKIN starts
again, the device will then lock to the valid input RxCLKIN and
then transmits the RGB data to the desializer. Note – in STOP
CLOCK SLEEP, the optional Serial Bus Control Registers
values are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS90UR907Q parallel control bus operate with 1.8 V or
3.3 V levels (V_DDIO) for host compatibility. The 1.8 V levels will
offer a system power savings.
OPTIONAL SERIAL BUS CONTROL
Please see the following section on the optional Serial Bus
Control Interface.
Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature sup-
ports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only a input
clock is required along with control to the DS90UR907Q and
deserializer BISTEN input pins. The DS90UR907Q outputs a
test pattern (PRBS7) and drives the link at speed. The dese-
rializer detects the PRBS7 pattern and monitors it for errors.
A PASS output pin toggles to flag any payloads that are re-
ceived with 1 to 24 errors. Upon completion of the test, the
result of the test is held on the PASS output until reset (new
BIST test or Power Down). A high on PASS indicates NO
ERRORS were detected. A Low on PASS indicates one or
more errors were detected. The duration of the test is con-
trolled by the pulse width applied to the deserializer BISTEN
pin.
Inter-operability is supported between this FPD-Link II device
and all FPD-Link II generations (Gen 1/2/3) — see respective
datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 19 for the BIST mode flow diagram.
Step 1: Place the DS90UR907Q in BIST Mode by setting Ser
BISTEN = H. The BIST Mode is enabled via the BISTEN pin.
An RxCLKIN is required for all the Ser options. When the de-
serializer detects the BIST mode pattern and command (DCA
and DCB code) the RGB and control signal outputs are shut
off.
Step 2: Place the pairing deserializer in BIST mode by setting
the BISTEN = H. The Des is now in the BIST mode and checks
the incoming serial payloads for errors. If an error in the pay-
load (1 to 24) is detected, the PASS pin will switch low for one
half of the clock period. During the BIST test, the PASS output
can be monitored and counted to determine the payload error
rate.
Step 3: To Stop the BIST mode, the deserializer BISTEN pin
is set Low. The deserializer stops checking the data and the
final test result is held on the PASS pin. If the test ran error
free, the PASS output will be High. If there was one or more
errors detected, the PASS output will be Low. The PASS out-
put state is held until a new BIST is run, the device is RESET,
or Powered Down. The BIST duration is user controlled by the
duration of the BISTEN signal.
Step 4: To return the link to normal operation, the
DS90UR907Q BISTEN input is set Low. The Link returns to
normal operation.
Figure 20 shows the waveform diagram of a typical BIST test
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data trans-
mission etc.), thus they may be introduced by greatly extend-
ing the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or dese-
rializer Equalization).
17
www.ti.com