AM3359_16 Datasheet, PDF (172/253 Pages) Texas Instruments – Sitara Processors

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
www.ti.com
7.7.2.3.3 DDR3 Interface
This section provides the timing specification for the DDR3 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR3 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR3
specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification application
report (SPRAAV0). This application report provides generic guidelines and approach. All the specifications
provided in the data manual take precedence over the generic guidelines and must be adhered to for a
reliable DDR3 interface operation.
7.7.2.3.3.1 DDR3 Interface Schematic
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 7-47
shows the schematic connections for 16-bit interface on AM335x device using one x16 DDR3 device and
Figure 7-49 shows the schematic connections for 16-bit interface on AM335x device using two x8 DDR3
devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The AM335x
device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads
connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see
Section 7.7.2.3.3.8.
172 Peripheral Information and Timings
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