AM3359_16 Datasheet, PDF (106/253 Pages) Texas Instruments – Sitara Processors

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
www.ti.com
6.1.4 Digital Phase-Locked Loop Power Supply Requirements
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the AM335x device. The AM335x device integrates 5 different DPLLs—Core DPLL, Per DPLL, Display
DPLL, DDR DPLL, MPU DPLL.
Figure 6-8 shows the power supply connectivity implemented in the AM335x device. Table 6-1 provides
the power supply requirements for the DPLL.
VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
MPU
PLL
CORE
PLL
LCD
PLL
PER
PLL
DDR
PLL
VDDA1P8V_USB0
VDDS_PLL_DDR
Figure 6-8. DPLL Power Supply Connectivity
SUPPLY NAME
VDDA1P8V_USB0
VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
Table 6-1. DPLL Power Supply Requirements
DESCRIPTION
Supply voltage range for USBPHY and PER DPLL, Analog, 1.8 V
Max peak-to-peak supply noise
Supply voltage range for DPLL MPU, analog
Max peak-to-peak supply noise
Supply voltage range for DPLL CORE and LCD, analog
Max peak-to-peak supply noise
Supply voltage range for DPLL DDR, analog
Max peak-to-peak supply noise
MIN NOM MAX UNIT
1.71 1.8 1.89 V
50 mV (p-p)
1.71 1.8 1.89 V
50 mV (p-p)
1.71 1.8 1.89 V
50 mV (p-p)
1.71 1.8 1.89 V
50 mV (p-p)
106 Power and Clocking
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