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AM3359_16 Datasheet, PDF (146/253 Pages) Texas Instruments – Sitara Processors | |||
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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J â OCTOBER 2011 â REVISED APRIL 2016
www.ti.com
Table 7-30. GPMC and NAND Flash Switching CharacteristicsâAsynchronous Mode
NO.
PARAMETER
OPP100
MIN
MAX
OPP50
UNIT
MIN
MAX
GNF0
tR(d)
tF(d)
tw(wenV)
GNF1 td(csnV-wenV)
GNF2 tw(cleH-wenV)
GNF3 tw(wenV-dV)
GNF4 tw(wenIV-dIV)
GNF5 tw(wenIV-cleIV)
GNF6 tw(wenIV-csnIV)
GNF7 tw(aleH-wenV)
GNF8 tw(wenIV-aleIV)
GNF9 tc(wen)
GNF10 td(csnV-oenV)
GNF13
GNF14
GNF15
tw(oenV)
tc(oen)
tw(oenIV-csnIV)
Rise time, output data gpmc_ad[15:0]
2
2 ns
Fall time, output data gpmc_ad[15:0]
2
2 ns
Pulse duration, output write enable gpmc_wen
A(1)
valid
A(1)
ns
Delay time, output chip select gpmc_csn[x](13)
valid to output write enable gpmc_wen valid
B(2) â 0.2 B(2) + 2.0
B(2) â 5
B(2) + 5 ns
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle high to
output write enable gpmc_wen valid
C(3) â 0.2 C(3) + 2.0
C(3) â 5
C(3) + 5 ns
Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid
D(4) â 0.2 D(4) + 2.0
D(4) â 5
D(4) + 5 ns
Delay time, output write enable gpmc_wen
invalid to output data gpmc_ad[15:0] invalid
E(5) â 0.2
E(5) + 5
E(5) â 5
E(5) + 5 ns
Delay time, output write enable gpmc_wen
invalid to output lower-byte enable and command
latch enable gpmc_be0n_cle invalid
F(6) â 0.2
F(6) + 2.0
F(6) â 5
F(6) + 5 ns
Delay time, output write enable gpmc_wen
invalid to output chip select gpmc_csn[x](13)
invalid
G(7) â 0.2 G(7) + 2.0
G(7) â 5
G(7) + 5 ns
Delay time, output address valid and address
latch enable gpmc_advn_ale high to output write
enable gpmc_wen valid
C(3) â 0.2 C(3) + 2.0
C(3) â 5
C(3) + 5 ns
Delay time, output write enable gpmc_wen
invalid to output address valid and address latch
enable gpmc_advn_ale invalid
F(6) â 0.2 F(6) + 2.0
F(6) â 5
F(6) + 5 ns
Cycle time, write
H(8)
H(8) ns
Delay time, output chip select gpmc_csn[x](13)
valid to output enable gpmc_oen valid
I(9) â 0.2 I(9) + 2.0
I(9) â 5
I(9) + 5 ns
Pulse duration, output enable gpmc_oen valid
K(10)
K(10)
ns
Cycle time, read
L(11)
L(11)
ns
Delay time, output enable gpmc_oen invalid to M(12) â 0.2 M(12) + 2.0 M(12) â 5 M(12) + 5 ns
output chip select gpmc_csn[x](13) invalid
(1) A = (WEOffTime â WEOnTime) Ã (TimeParaGranularity + 1) Ã GPMC_FCLK(14)
(2) B = ((WEOnTime â CSOnTime) Ã (TimeParaGranularity + 1) + 0.5 Ã (WEExtraDelay â CSExtraDelay)) Ã GPMC_FCLK(14)
(3) C = ((WEOnTime â ADVOnTime) Ã (TimeParaGranularity + 1) + 0.5 Ã (WEExtraDelay â ADVExtraDelay)) Ã GPMC_FCLK(14)
(4) D = (WEOnTime à (TimeParaGranularity + 1) + 0.5 à WEExtraDelay) à GPMC_FCLK(14)
(5) E = ((WrCycleTime â WEOffTime) Ã (TimeParaGranularity + 1) â 0.5 Ã WEExtraDelay) Ã GPMC_FCLK(14)
(6) F = ((ADVWrOffTime â WEOffTime) Ã (TimeParaGranularity + 1) + 0.5 Ã (ADVExtraDelay â WEExtraDelay)) Ã GPMC_FCLK(14)
(7) G = ((CSWrOffTime â WEOffTime) Ã (TimeParaGranularity + 1) + 0.5 Ã (CSExtraDelay â WEExtraDelay)) Ã GPMC_FCLK(14)
(8) H = WrCycleTime à (1 + TimeParaGranularity) à GPMC_FCLK(14)
(9) I = ((OEOnTime â CSOnTime) Ã (TimeParaGranularity + 1) + 0.5 Ã (OEExtraDelay â CSExtraDelay)) Ã GPMC_FCLK(14)
(10) K = (OEOffTime â OEOnTime) Ã (1 + TimeParaGranularity) Ã GPMC_FCLK(14)
(11) L = RdCycleTime à (1 + TimeParaGranularity) à GPMC_FCLK(14)
(12) M = ((CSRdOffTime â OEOffTime) Ã (TimeParaGranularity + 1) + 0.5 Ã (CSExtraDelay â OEExtraDelay)) Ã GPMC_FCLK(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
146 Peripheral Information and Timings
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