THS4303_14 Datasheet, PDF (17/30 Pages) Texas Instruments – WIDEBAND FIXED-GAIN AMPLIFIER

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to the caps, and 3 or more vias to connect the
caps to the ground plane.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Solid power planes can lead to PCB resonances
when they are not properly terminated to the
ground plane over the area and along the per-
imeter of the power plane by high frequency
capacitors. Doing so assures that there are no
power plane resonances in the needed frequency
range. Values used are in the range of 2 pF - 50
pF, depending on the frequencies to be sup-
pressed, with numerous vias for each.
4. Using 0402 or smaller component sizes is rec-
ommended. An approximate expression for the
resonate frequencies associated with a length of
one of the power plane dimensions is given in
equation (1). Note that a power plane of arbitrary
shape can have a number of resonant fre-
quencies. A power plane without distributed ca-
pacitors and with active parts near the center of
the plane usually has n even (≥2) due to the half
wave resonant nature of the plane.
n (44 GHz mm)
frequency_res [
ȏ
where:
frequency_res = the approximate power plane resonant
frequencies in GHz
ȏ^{= the length of the power plane dimensions in}
millimeters
n = an integer (n > 1) related to the mode of the oscillation
• For guidance on capacitor spacing over the area
of the ground plane, specify the lowest resonant
frequency to be tolerated, then solve for in
equation (1) above, with n = 2. Use this length for
the capacitor spacing. It is recommended that a
power plane, if used, be either small enough, or
decoupled as described, so that there are no
resonances in the frequency range of interest. An
alternative is to use a ferrite bead outside of the
opamp high frequency bypass caps to decouple
the amplifier, and mid and high frequency bypass
capacitors, from the power plane. When a trace is
used to deliver power, its self-resonance is given
approximately by equation (1), substituting the
trace length for power plane dimension.
1. Bypass capacitors, since they have a
self-inductance, resonate with each other. To
achieve optimum transfer characteristics through
2 GHz, it is recommended that the bypass
arrangement employed in the prototype board be
used. The 30.1-Ω resistor in series with the
0.1-µF capacitor reduces the Q of the resonance
of the lumped parallel elements including the
0.1-µF and 47-pF capacitors, and the power
supply input of the amplifier. The ferrite bead
isolates the low frequency 22-µF capacitor and
THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
power plane from the remainder of the bypass
network.
2. By removing the 30.1-Ω resistor and ferrite bead,
the frequency response characteristic above 400
MHz may be modified. However, bandwidth, dis-
tortion, and transient response remain optimal.
3. Recommended values for power supply decoup-
ling include a bulk decoupling capacitor (22 µF),
a ferrite bead with a high self-resonant frequency,
a mid-range decoupling capacitor (0.1 µF) in
series with a 30.1-Ω resistor, and a high fre-
quency decoupling capacitor (47 pF).
BOARD LAYOUT
Printed-Circuit Board Layout Techniques for Opti-
mal Performance
Achieving optimum performance with a high fre-
quency amplifier like the THS4303 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. However,
if using a transmission line at the I/O, then place
the matching resistor as close to the part as
possible. Except for when transmission lines are
used, parasitic capacitance on the output and the
noninverting input pins can react with the load
and source impedances to cause unintentional
band limiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be
opened in all of the ground and power planes
around those pins. Otherwise, ground planes and
power planes (if used) should be unbroken else-
where on the board, and terminated as described
in the Power Supply Decoupling section.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. Note that each millimeter of a line,
that is narrow relative to its length, has ~ 0.8 nH
of inductance. The power supply connections
should always be decoupled with the rec-
ommended capacitors. If not properly decoupled,
distortion performance is degraded. Larger
(6.8-µF to 22-µF) decoupling capacitors, effective
at lower frequency, should also be used on the
main supply lines, preferably decoupled from the
amplifier and mid and high frequency capacitors
by a ferrite bead. Reference the Power Supply
Decoupling Techniques section. The larger caps
may be placed somewhat farther from the device
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