THS4303_14 Datasheet, PDF (16/30 Pages) Texas Instruments – WIDEBAND FIXED-GAIN AMPLIFIER

THS4303
SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005
The second circuit depicts single-ended ADC drive.
While not recommended for optimum performance
using converters with differential inputs, satisfactory
performance can sometimes be achieved with single-
ended input drive. An example circuit is shown here
for reference.
V_S+
+
FB
22 µF
50 Ω Source
R_f
R_g
_
47 pF
0.1 µF
30.1 Ω
*2.5 V
V_I
+ _THS4303
49.9 Ω
*2.5 V
FB = Ferrite Bead
* = Low Impedance
R_ISO ^C
C
R
IN
ADC
CM
IN
C
Figure 46. Driving an ADC With a Single-Ended
Input
NOTE:
For best performance,
high-speed ADCs should
be driven differentially.
See the THS4500 family
of devices for more infor-
mation.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
High-speed amplifiers like the THS4303 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
directly on the output pin. When the amplifier's
open-loop output resistance is considered, this ca-
pacitive load introduces an additional pole in the
signal path that can decrease the phase margin.
When the primary considerations are frequency re-
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sponse flatness, pulse response fidelity, or distortion,
the simplest and most effective solution is to isolate
the capacitive load from the feedback loop by in-
serting a series isolation resistor between the ampli-
fier output and the capacitive load.
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4303. Long PC board traces,
unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4303 output pin (see Board Layout
Guidelines).
The criterion for setting this R_(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load.
22
R_L = 100 Ω
V_S = 5 V
20
R_ISO = 25 Ω, C_L = 10 pF
18
R_ISO = 15 Ω, C_L = 47 pF
16
R_ISO= 10 Ω, C_L = 100 pF
14
12
10
1M
−
RISO
+
CL
10 M
100 M
1G
f − Frequency − Hz
Figure 47. Driving Capacitive Loads
POWER SUPPLY DECOUPLING TECHNIQUES
AND RECOMMENDATIONS
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of per-
formance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply. Inductance in series
with the bypass capacitors will degrade perform-
ance. Note that a narrow lead or trace has about
0.8 nH of inductance for every millimeter of
length. Each printed-circuit board (PCB) via also
has between 0.3 and 0.8 nH depending on length
and diameter. For these reasons, it is rec-
ommended to use a power supply trace about the
width of the package for each power supply lead
16