LM3S2730 Datasheet, PDF (160/562 Pages) Texas Instruments – Stellaris® LM3S2730 Microcontroller

JTAG Interface
4.5.2.4
4.5.2.5
4.5.2.6
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 4-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
... I
N
O
U
T
O
E
I
N
I
N
O
U
T
O
E
... I
N
O
U
T
O TDO
E
GPIO PB6
GPIO m
RST
GPIO m+1
GPIO n
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
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June 18, 2012
Texas Instruments-Production Data