LMD18400 Datasheet, PDF (16/26 Pages) National Semiconductor (TI) – Quad High Side Driver

LMD18400
SNVS094C – JUNE 1996 – REVISED APRIL 2013
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Figure 28. Load Resistance Detected as Errors
THERMAL MANAGEMENT
It is particularly important to consider the total amount of power being dissipated by all four switches in the
LMD18400 at all times. Any combination of the switches driving loads will cause an increase in the die
temperature. Should the die temperature reach the thermal shutdown threshold of +170°C, all of the switches will
be disabled.
Careful calculation of the worst case total power dissipation required at any point in time, together with providing
sufficient heatsinking will prevent this from occurring.
The LMD18400 is packaged with a special leadframe that helps dissipate heat through the two ground pins on
each side of the package. The thermal resistance from junction-to-case (θ_JC) for this package is approximately
20°C/W. The thermal resistance from junction-to-ambient (θ_JA), without any heatsinking, is approximately
60°C/W. Figure 29 illustrates how the copper foil of a printed circuit board can be designed to provide
heatsinking and reduce the overall junction-to-ambient thermal resistance.
The power dissipation in each switch is equal to:
where
• R_ON is the ON resistance of the switch (1.3Ω maximum)
(4)
These equations hold true until the power dissipation reaches the maximum limit of 15W. With resistive loads,
the 15W power limit threshold will be reached when:
(5)
Inductive loads will create additional power dissipation when switched OFF. Figure 30 shows the idealized
voltage and current waveforms for an inductive load.
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