LMD18400 Datasheet, PDF (11/26 Pages) National Semiconductor (TI) – Quad High Side Driver

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LMD18400
SNVS094C – JUNE 1996 – REVISED APRIL 2013
Figure 20. Overvoltage/Undervoltage Shutdown
The LMD18400 has been designed to drive all types of loads. When driving a ground referenced inductive load
such as a relay or solenoid, the voltage across the load will reverse in polarity as the field in the inductor
collapses when the power switch is turned OFF. This will pull the output pin of the LMD18400 below ground. This
negative transient voltage is clamped at approximately −5V to protect the IC. This clamping action is not done
with diodes but rather the power DMOS switch turning back on momentarily to conduct the inductor current as it
de-energizes as shown in Figure 21.
Figure 21. Turn-OFF Conditions with an Inductive Load
When the output inductance produces a negative voltage, the gate of the DMOS transistor is clamped at 0V. At
−3.5V, the source of the power device is less than the gate by enough to cause the switch to turn ON again.
During this negative transient condition the power limiting circuitry to protect the switch is disabled due to the
gate being held at 0V. The maximum current during this clamping interval, which is equal to the steady state ON
current through the inductor, should be kept less than 1A. Another concern during this interval has to do with the
size of an inductive load and the amount of time required to de-energize it. With larger inductors it may be
possible for the additional power dissipation to cause the die temperature to exceed the thermal shutdown limit. If
this occurs all of the other switches will turn OFF momentarily (see section on THERMAL MANAGEMENT).
Power Limiting
The LMD18400 utilizes a true instantaneous power limit circuit rather than simple current limiting to protect each
switch. This provides a higher transient current capability while still maintaining a safe power dissipation level.
The power dissipation in each switch (the product of the Drain-to-Source voltage and the output current, V_ds ×
I_OUT) is continually monitored and limited to 15W by varying the gate voltage and therefore the ON resistance of
the switch. Basically the ON resistance will be as low as possible until 15W is being dissipated. To maintain
15W, the ON resistance increases to reduce the load current. This results in a decrease of the output voltage.
For resistive loads, the output voltage when in power limit will be:
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