LMD18400 Datasheet, PDF (10/26 Pages) National Semiconductor (TI) – Quad High Side Driver

LMD18400
SNVS094C – JUNE 1996 – REVISED APRIL 2013
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Figure 19. Control Logic for Each Power Switch
Each DMOS switch is turned ON when its gate is driven approximately 3.5V more positive than its source
voltage. Because the source of the switch is the output terminal to the load it can be taken to a voltage very near
the V_CC supply potential. To ensure that there is sufficient voltage available to drive the gates of the DMOS
device a charge pump circuit is built in. This circuit is controlled by an internal 300 kHz oscillator and using an
external 10 nF capacitor connected from pin 14 to ground generates a voltage that is approximately 20V greater
than the V_CC supply voltage. This provides sufficient gate voltage drive for each of the switches which is applied
under command of standard 5V logic input levels.
The turn-on time for each switch is approximately 12 µs when driving a 1A load current. This relatively slow
switching time is beneficial in minimizing electromagnetic interference (EMI) related problems created from
switching high current levels.
PROTECTION CIRCUITRY
The LMD18400 has extensive protection circuitry built in. With any power device, protection against excessive
voltage, current and temperature conditions is essential. To achieve a “fail-safe” system implementation, the
loads are deactivated automatically by the LMD18400 in the event of any detected overvoltage or over-
temperature fault conditions.
Voltage Protection
The V_CC supply can range from −0.5V to +60 V_DC without any damage to the LMD18400. The CMOS logic
circuitry is biased from an internal 5.1V regulator which protects these lower voltage transistors from the higher
V_CC potentials. In order to protect the loads connected to the switch outputs however, an overvoltage shutdown
circuit is employed. Should the V_CC potential exceed 35V all of the switches are turned OFF thereby
disconnecting the loads. This 35V threshold has 750 mV of hysteresis to prevent potential oscillations.
Additionally, there is an undervoltage lockout feature built in. With V_CC less than 5V it becomes uncertain
whether the logic circuitry can hold the switches in their commanded state. To avoid this uncertainty, all of the
switches are turned OFF when V_CC drops below approximately 5V. Figure 20 illustrates the shutoff of an output
during a 0V to 80V V_CC supply transient.
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