HD3SS214_16 Datasheet, PDF (16/25 Pages) Texas Instruments – 8.1 Gbps DisplayPort 1.3 2:1/1:2 Differential Switch

HD3SS214
SLAS907A – DECEMBER 2015 – REVISED JULY 2016
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9 Power Supply Recommendations
There is no power supply sequence required for HD3SS214. However, it is recommended that OE is asserted
high after device supply VDD is stable and in spec. It is also recommended that ample decoupling capacitors are
placed at the device VCC near the pin.
10 Layout
10.1 Layout Guidelines
10.1.1 Layer Stack
Routing the high-speed differential signal traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects from the DisplayPort connectors to the repeater inputs and
from the repeater output to the subsequent receiver circuit.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
Routing the fast-edged control signals on the bottom layer by prevents them from cross-talking into the high-
speed signal traces and minimizes EMI.
If the receiver requires a supply voltage different from the one of the repeater, add a second power/ground plane
system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from
warping. Also, the power and ground plane of each power system can be placed closer together, thus increasing
the high-frequency bypass capacitance significantly. Finally, a second power/ground system provides added
isolation between the signal layers.
5 to 10 mils
Layer 1: High-speed, differential
signal traces
Layer 2: Ground plane
Layer 1: High-speed, differential
signal traces
Layer 2: Ground
Layer 3: V_CC1
20 to 40 mils
5 to 10 mils
Layer 3: Power plane
Layer 4: Low-frequency,
single-ended traces
Layer 4: V_CC2
Layer 5: Ground
Layer 6: Low-frequency,
single-ended traces
Figure 9. Recommended 4- or 6- Layer (0.062") Stack for a Receiver PCB Design
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