CD4051B_15 Datasheet, PDF (16/38 Pages) Texas Instruments – CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

CD4051B, CD4052B, CD4053B
SCHS047H – AUGUST 1998 – REVISED APRIL 2015
8 Detailed Description
www.ti.com
8.1 Overview
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low
ON impedance and very low OFF leakage current. Control of analog signals up to 20 V_P-P can be achieved by
digital signal amplitudes of 4.5 V to 20 V (if V_DD – V_SS = 3 V, a V_DD – V_EE of up to 13 V can be controlled; for
V_DD – V_EE level differences above 13 V, a V_DD – V_SS of at least 4.5 V is required). For example, if V_DD = +4.5 V,
V_SS = 0 V, and V_EE = –13.5 V, analog signals from –13.5 V to +4.5 V can be controlled by digital inputs of 0 V to
5 V. These multiplexer circuits dissipate extremely low quiescent power over the full V_DD – V_SS and V_DD – V_EE
supply-voltage ranges, independent of the logic state of the control signals. When a logic 1 is present at the
inhibit input terminal, all channels are off.
The CD4051B device is a single 8-channel multiplexer having three binary control inputs, A, B, and C, and an
inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to
the output.
The CD4052B device is a differential 4-channel multiplexer having two binary control inputs, A and B, and an
inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog
inputs to the outputs.
The CD4053B device is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C,
and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
8.2 Functional Block Diagrams
16 V_DD
CHANNEL IN/OUT
76543210
4 2 5 1 12 15 14 13
TG
A 11
B 10
C9
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
TG
TG
COMMON
TG
OUT/IN
3
TG
TG
TG
INH 6
TG
8 V_SS
7 V_EE
All inputs are protected by standard CMOS protection network.
Figure 25. Functional Block Diagram, CD4051B
16
Submit Documentation Feedback
Copyright © 1998–2015, Texas Instruments Incorporated
Product Folder Links: CD4051B CD4052B CD4053B