BQ2961_17 Datasheet, PDF (16/33 Pages) Texas Instruments – Overvoltage Protection for 2-Series, 3-Series, and 4-Series Cell Li-Ion Batteries with Regulated Output Supply

bq2961, bq2962
SLUSBU5D – NOVEMBER 2013 – REVISED JANUARY 2017
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Device Functional Modes (continued)
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceed the overvoltage threshold, V_OV, for
configured OV delay time. The OUT pin is activated after a delay time preprogrammed at the factory. The OUT
pin will pull high internally. Then an external FET is turned on, shorting the fuse to ground, which allows the
battery and/or charger power to blow the fuse. When all of the cell voltages fall below (V_OV – V_HYS), the device
returns to NORMAL mode. The regulated output (if enabled) remains on in this mode.
8.4.3 UNDERVOLTAGE Mode
The UNDERVOLTAGE mode is detected if any of the cell voltage across (V1–VSS), (V2–V1), (V3–V2), or
(V4–V3) is below the V_UVREG threshold for t_{UV_DELAY} time. In this mode, the regulated output is disabled. To return
to the NORMAL mode, all the cell voltages must be above (V_UVREG + V_UVHYS).
For a low cell configuration, V_n pin can be shorted to the (V_{n – 1}) pin. The device ignores any differential cell
voltage below V_UVQUAL threshold for undervoltage detection.
8.4.4 CUSTOMER TEST MODE
The Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay-timer parameter
once the circuit is implemented into the battery pack. To enter CTM, the VDD pin should be set at least 10 V
higher than V3 (see Figure 14). The delay timer is greater than 10 ms, but considerably shorter than the timer
delay in normal operation. To exit CTM, remove the VDD to VC3 voltage differential of 10 V, so that the
decrease in the value automatically causes an exit.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the
device into CTM. Also avoid exceeding Absolute Maximum Voltages for the individual
cell voltages (V3–V2), (V2–V1) and (V1–VSS). Stressing the pins beyond the rated
limits can cause permanent damage to the device.
Figure 14 shows the timing for the Customer Test Mode.
VDD ± V3 = 10V
VDD
V3
OUT (V)
> 10ms
Figure 14. Timing for Customer Test Mode
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