TMS320DM8148_13 Datasheet, PDF (158/370 Pages) Texas Instruments – TMS320DM814x DaVinci™Video Processors

TMS320DM8148, TMS320DM8147, TMS320DM8146
SPRS647D – MARCH 2011 – REVISED SEPTEMBER 2012
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Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin
functions are called Multimuxed (MM) and may have different Switching Characteristics and Timing
Requirements for each device pin option. The Multimuxed peripheral pin functions are labeled as "MM" in
Terminal Functions tables in Section 3.2, Terminal Functions and the associated timings for each MM pin
option are in Section 8, Peripheral Information and Timings.
For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers
breakout, see Figure 4-1 and Table 4-11. For the register reset values of each PINCNTLx register, see
Table 4-13, PINCNTLx Registers MUXMODE Functions.
Figure 4-1. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout
31
24
RESERVED
R - 0000 0000
15
8
RESERVED
R - 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
23
20
19
18
17
16
RESERVED
RSV
RSV PLLTY PLLU
PESE DEN
L
R - 0000
R/W - (see Table 4-13 for
register reset value)
7
0
MUXMODE[7:0] (see Table 4-13)
R/W - 0000 0000
Bit
31:20
19
18
17
16
15:8
7:0
Table 4-11. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions
Field
RESERVED
RSV
RSV
PLLTYPSEL
PLLUDEN
RESERVED
MUXMODE[7:0]
Description
Reserved. Read only, writes have no effect.
Reserved. This bit must always be written with the
reset (default) value.
(See Table 4-13 for full register reset value)
Reserved. This field must always be written as "1".
Pullup/Pulldown Type Selection bit
0 = Pulldown (PD) selected
1 = Pullup (PU) selected
Pullup/Pulldown Enable bit
0 = PU/PD enabled
1 = PU/PD disabled
Reserved. Read only, writes have no effect.
MUXMODE Selection bits
These bits select the multiplexed mode pin function
settings (seeTable 4-13, PINCNTLx Registers
MUXMODE Functions). Values other than those
shown inTable 4-13 are illegal.
Comments
For PINCNTLx register reset value
examples, see Table 4-12,
PNICNTLx Register Reset Value
Examples.
For the full register reset values of all
PINCNTLx registers, see Table 4-13,
PINCNTLx Registers MUXMODE
Functions.
158 Device Configurations
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