TMS320F2810 Datasheet, PDF (154/172 Pages) Texas Instruments – Digital Signal Processors

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)⁽¹⁾
MASTER
SLAVE
NO.
UNIT
MIN MAX
MIN MAX
M39
M40
M41
M42
t_su(DRV-CKXH)
t_h(CKXH-DRV)
t_su(FXL-CKXH)
t_c(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
2P
16P
ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)⁽¹⁾
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
M34 t_h(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35 t_d(FXL-CKXH)
Delay time, FSX low to CLKX high
2P
ns
M37 t_{dis(CKXL-DXHZ)}
Disable time, DX high impedance following last data bit
from CLKX low
P+6
7P + 6
ns
M38 t_d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
CLKX
FSX
DX
DR
LSB
M41
MSB
M42
M34
M35
M37
Bit 0
Bit 0
M38
M39
Bit(n-1)
Bit(n-1)
(n-2)
M40
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
154 Electrical Specifications
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