TMS320F2810 Datasheet, PDF (121/172 Pages) Texas Instruments – Digital Signal Processors

www.ti.com
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
1
2
3
6
7
Master Out Data Is Valid
10
11
Master In Data
Must Be Valid
Data Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5t_c(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5t_c(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays
active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-27. SPI Master External Timing (Clock Phase = 1)
Copyright © 2001–2012, Texas Instruments Incorporated
Electrical Specifications 121
Submit Documentation Feedback
Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812