VSP5010 Datasheet, PDF (15/25 Pages) Texas Instruments – 12-Bit, 31-MSPS, Dual-Channel CCD ANALOG FRONT-END FOR DIGITAL COPIERS

VSP5010
www.ti.com ................................................................................................................................................................................................ SBES014 – AUGUST 2008
The converging time of the OB loop is determined based on the capacitor value connected to the COB terminal
and the output from the current output digital-to-analog converter (DAC) of the loop. The time constant (T) can be
obtained from Equation 1:
T = C/(16384 ´ I_MIN)
(1)
Where:
• C is the capacitor value connected to COB,
• I_MIN is the minimum current (0.15 µA) of the current DAC, which has a current equivalent to 1 LSB of the
DAC converter output.
When C = 0.1 µF, T is 40.7 µs.
The slew rate (SR) can be obtained from Equation 2:
SR = I_MAX/C
(2)
Where:
• C is the capacitor value connected to COB,
• I_MAX is the maximum current (153 µA) of the current DAC, which is the equivalent current to 1023 LSB of
the DAC converter output.
The OB clamp level (digital output value) can be set externally through the serial interface by inputting a digital
code to the OB clamp level register. The digital code to be input and the corresponding OB clamp level are
shown in Table 2.
Table 2. Input Code and OB Clamp Level to be Set
CODE
0000 0000b
0000 0001b
—
0100 1111b
0101 0000 (default)
0101 0001b
—
1011 1111b
1111 1111b
CLAMP LEVEL (LSB)
VSP5010 (12-BIT)
0
2
—
158
160
162
—
508
510
SETTLING OF OB LOOP AND INPUT CLAMP
Because these capacitors are discharged at start-up and after a long standby state, these two capacitors must
be charged to the proper operational voltage.
The charging time for the input clamp voltage is the logical AND of SHP (SHD in S/H mode) and INPUTCLP. The
actual charging time per line is the duration of the SHP pulse times the number of dummy pixels in the line.
Equally, COB is only charged during the OB pixel period. Therefore, some time is necessary to bring the
VSP5010 into a normal operating state at device start-up.
Though start-up time depends on the number of dummy and pixels per line, at least 500 ms to 1 s should be
allowed.
STANDBY MODE
Normal operation mode and standby mode can be switched by the serial interface.
In standby mode, power consumption can be saved; all operation is suspended other than the interface circuit
and reference voltage supply. During standby mode, additional power consumption may be obtained by
suspending SYSCLK. When restoring a SYSCLK that was suspended during standby mode, more than two
clocks of SYSCLK must be acquired before inputting commands.
Copyright © 2008, Texas Instruments Incorporated
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