TLC320AD545 Datasheet, PDF (15/37 Pages) Texas Instruments – Single Channel Data/Fax Codec

3 Codec Functional Description
3.1 Operating Frequencies
The TLC320AD545 is capable of supporting any sample rate up to the maximum sample rate of 11.025 kHz. The
sample rate is set by the frequency of the codec master clock.
The sampling (conversion) frequency is derived from the codec master clock by the internal clock divider circuit by
equation (1):
DT_FS= Sampling (conversion) frequency = DT_MCLK/512
(1)
The shift clock (SCLK) is derived from the codec master clock divider circuit by equation (2):
DT_SCLK (frequency)= DT_MCLK/2
(2)
Where MCLK is codec clock fed to the codec externally by the clock rate divider circuit which divides the system
master clock to get the necessary clock frequency to feed the codec.
The conversion period is the inverse of sampling frequency.
3.2 ADC Signal Channel
The input signals are amplified and filtered by on-chip buffers before being applied to ADC input. The ADC converts
the signal into discrete output digital words in 2s-complement format, corresponding to the analog signal value at the
sampling time. These 16-bit digital words, representing sampled values of the analog input signal, are sent to the host
through the serial port interface. If the ADC reaches its maximum value, a control register flag is set. This overflow
bit resides at D0 in control register 2. This bit can only be read from the serial port, and the overflow flag is only cleared
if it is read through the serial port. The ADC and DAC conversions are synchronous and phase-locked.
3.3 DAC Signal Channel
The DAC receives 16-bit data words (2s complement) from the host through the serial port interface. The data is
converted to an analog voltage by the sigma-delta DAC comprised of a digital interpolation filter and a digital
modulator. The DAC output is then passed to an internal low-pass filter to complete the signal reconstruction resulting
in an analog signal. This analog signal is then buffered and amplified by differential output driver capable of driving
the required load. The gain of the DAC output amplifier is programmed by the codec control register as shown in
Appendix A.
3.4 Sigma-Delta ADC
The ADC is an oversampling sigma-delta modulator. The ADC provides high resolution and low noise performance
using oversampling techniques and the noise shaping advantages of sigma-delta modulators.
3.5 Decimation Filter
The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating with a ratio
equal to the oversampling ratio. The output of this filter is a sixteen-bit 2s-complement data word clocking at the
selected sample rate.
3.6 Sigma-Delta DAC
The DAC is an oversampling sigma-delta modulator. The DAC perform high-resolution, low-noise digital-to-analog
conversion using oversampling sigma-delta techniques.
3–1