BQ2012_15 Datasheet, PDF (15/26 Pages) Texas Instruments – Gas Gauge IC With Slow-Charge Control

Not Recommended For New Designs
bq2012
Digital Magnitude Filter (DMF)
The read-write DMF register (address = 0ah) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different val-
ues into this register, the limits of VSRD and VSRQ can be
adjusted.
Note: Care should be taken when writing to this regis-
ter. A VSRD and VSRQ below the specified VOS may ad-
versely affect the accuracy of the bq2012. Refer to Table
4 for recommended settings for the DMF register.
Reset Register (RST)
The reset register (address=39h) provides the means to
perform a software-controlled reset of the device. By
writing the RST register contents from 00h to 80h, a
bq2012 reset is performed. Setting any bit other than the
most-significant bit of the RST register is not allowed,
and results in improper operation of the bq2012.
Resetting the bq2012 sets the following:
I LMD = PFC
I CPI, VDQ, NACH, and NACL = 0
I CI and BRP = 1
Note: NACH = PFC when PROG6 = H.
Display
The bq2012 can directly display capacity information us-
ing low-power LEDs. If LEDs are used, the program
pins should be resistively tied to VCC or VSS for a pro-
gram high or program low, respectively.
The bq2012 displays the battery charge state in either
absolute or relative mode. In relative mode, the battery
charge is represented as a percentage of the LMD. Each
LED segment represents 20% of the LMD. The sixth
segment is not used.
In absolute mode, each segment represents a fixed
amount of charge, based on the initial PFC. In absolute
mode, each segment represents 20% of the PFC, with
the sixth segment representing “overfull” (charge above
the PFC). As the battery wears out over time, it is pos-
sible for the LMD to be below the initial PFC. In this
case, all of the LEDs may not turn on, representing the
reduction in the actual battery capacity.
The capacity display is also adjusted for the present bat-
tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
not affect the NAC register. The temperature adjust-
ments are detailed in the TMPGG register description.
When DISP is tied to VCC, the SEG1–6 outputs are inac-
tive. When DISP is left floating, the display becomes ac-
tive whenever the NAC registers are counting at a rate
equivalent to VSRO < -4mV or VSRO > VSRQ. When
pulled low, the segment outputs become active immedi-
ately. A capacitor tied to DISP allows the display to re-
main active for a short period of time after activation by
a push-button switch.
The segment outputs are modulated as two banks of
three, with segments 1, 3, and 5 alternating with seg-
ments 2, 4, and 6. The segment outputs are modulated
at approximately 100Hz with each segment bank active
for 30% of the period.
SEG1 blinks at a 4Hz rate whenever VSB has been de-
tected to be below VEDV1 (EDV1 = 1), indicating a low-
battery condition. VSB below VEDVF (EDVF = 1) disables
the display output.
Microregulator
The bq2012 can operate directly from three or four cells.
To facilitate the power supply requirements of the
bq2012, an REF output is provided to regulate an exter-
nal low-threshold n-FET. A micropower source for the
bq2012 can be inexpensively built using the FET and an
external resistor; see Figure 1.
15