BQ2012_15 Datasheet, PDF (14/26 Pages) Texas Instruments – Gas Gauge IC With Slow-Charge Control

Not Recommended For New Designs
bq2012
of the battery from full to empty. In this way the
bq2012 updates the capacity of the battery. LMD is set
to PFC during a bq2012 reset.
DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to VSS. The rate at which
this measurement is made varies with device activity.
Secondary Status Flags Register (FLGS2)
The read-only FLGS2 register (address=06h) contains
the secondary bq2012 flags.
The charge rate flag (CR) is used to denote the fast
charge regime. Fast charge is assumed whenever a
charge action is initiated. The CR flag remains asserted
if the charge rate does not fall below 2 counts/sec.
The CR values are:
FLGS2 Bits
7
65
4
3
2
1
0
CR - -
-
-
-
-
-
Where CR is:
0 When charge rate falls below 2 counts/sec
1 When charge rate is above 2 counts/sec
The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac-
tors are used. The time to change CR varies due to the
user-selectable count rates.
The discharge rate flags, DR2–0, are bits 6–4.
FLGS2 Bits
7
6
5
4
3210
-
DR2 DR1 DR0 - - -
They are used to determine the current discharge re-
gime as follows:
DR2
0
0
DR1
0
0
DR0
0
1
VSR (V)
VSR > -150mV
VSR < -150mV
The overload flag (OVLD) is asserted when a discharge
overload is detected, VSR < -250mV. OVLD remains as-
serted as long as the condition persists and is cleared
when VSR > -250mV. The overload condition is used to
stop sampling of the battery terminal characteristics for
end-of-discharge determination. Sampling is re-enabled
0.5 secs after the overload condition is removed.
FLGS2 Bits
7
65
4
3
2
-
--
-
-
-
1
0
- OVLD
Program Pin Pull-Down Register (PPD)
The read-only PPD register (address=07h) contains some of
the programming pin information for the bq2012. The seg-
ment drivers, SEG1–6, have a corresponding PPD register
location, PPD1–6. A given location is set if a pull-down re-
sistor has been detected on its corresponding segment
driver. For example, if SEG1 and SEG4 have pull-down
resistors, the contents of PPD are xx001001.
Program Pin Pull-Up Register (PPU)
The read-only PPU register (address=08h) contains the
rest of the programming pin information for the
bq2012. The segment drivers, SEG1–6, have a corre-
sponding PPU register location, PPU1–6. A given loca-
tion is set if a pull-up resistor has been detected on its cor-
responding segment driver. For example, if SEG3 and
SEG6 have pull-up resistors, the contents of PPU are
xx100100.
PPD/PPU Bits
8
7
6
5
4
3
2
1
-
- PPU6 PPU₅ PPU4 PPU3 PPU2 PPU1
-
- PPD6 PPD₅ PPD4 PPD3 PPD2 PPD1
Capacity Inaccurate Count Register (CPI)
The read-only CPI register (address=09h) is used to in-
dicate the number of times a battery has been charged
without an LMD update. Because the capacity of a re-
chargeable battery varies with age and operating condi-
tions, the bq2012 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.
The CPI register is incremented every time a valid
charge is detected if NAC < 0.94 _* LMD. When NAC ≥
0.94 _* LMD, the CPI register increments on the first
valid charge; CPI does not increment again for a valid
charge until NAC is discharged below 0.94 _* LMD. This
prevents continuous trickle charging from incrementing
CPI if self-discharge decrements NAC. The CPI register
increments to 255 without rolling over. When the con-
tents of CPI are incremented to 64, the capacity inaccu-
rate flag, CI, is asserted in the FLGS1 register. The CPI
register is reset whenever an update of the LMD regis-
ter is performed, and the CI flag is also cleared.
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