TM4C123BE6PZ_15 Datasheet, PDF (141/1310 Pages) Texas Instruments – Tiva TM4C123BE6PZ Microcontroller

Tiva^™ TM4C123BE6PZ Microcontroller
Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204
Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208
Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C
Note: This register can only be accessed from privileged mode.
The PENDn registers force interrupts into the pending state and show which interrupts are pending.
Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1
corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to
Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31
corresponds to Interrupt 127. Bit 0 of PEND4 (see page 142) corresponds to Interrupt 128; bit 10
corresponds to Interrupt 138.
See Table 2-9 on page 99 for interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
INT
Type
Reset Description
RW 0x0000.0000 Interrupt Set Pending
Value
0
1
Description
On a read, indicates that the interrupt is not pending.
On a write, no effect.
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
June 12, 2014
141
Texas Instruments-Production Data