TM4C123BE6PZ_15 Datasheet, PDF (12/1310 Pages) Texas Instruments – Tiva TM4C123BE6PZ Microcontroller

Table of Contents
Figure 11-7. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 717
Figure 11-8. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 717
Figure 11-9. Timer Daisy Chain ............................................................................................. 718
Figure 12-1. WDT Module Block Diagram .............................................................................. 774
Figure 13-1. Implementation of Two ADC Blocks .................................................................... 799
Figure 13-2. ADC Module Block Diagram ............................................................................... 800
Figure 13-3. ADC Sample Phases ......................................................................................... 804
Figure 13-4. Doubling the ADC Sample Rate .......................................................................... 804
Figure 13-5. Skewed Sampling .............................................................................................. 805
Figure 13-6. Sample Averaging Example ............................................................................... 806
Figure 13-7. ADC Input Equivalency ...................................................................................... 807
Figure 13-8. ADC Voltage Reference ..................................................................................... 808
Figure 13-9. ADC Conversion Result ..................................................................................... 809
Figure 13-10. Differential Voltage Representation ..................................................................... 811
Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 812
Figure 13-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 814
Figure 13-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 815
Figure 13-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 816
Figure 14-1. UART Module Block Diagram ............................................................................. 898
Figure 14-2. UART Character Frame ..................................................................................... 900
Figure 14-3. IrDA Data Modulation ......................................................................................... 902
Figure 15-1. SSI Module Block Diagram ................................................................................. 959
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 963
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 964
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 965
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 965
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 966
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 967
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 967
Figure 15-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 968
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 969
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 970
Figure 15-12. MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 970
Figure 16-1. I²C Block Diagram ........................................................................................... 1004
Figure 16-2. I²C Bus Configuration ....................................................................................... 1005
Figure 16-3. START and STOP Conditions ........................................................................... 1006
Figure 16-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1006
Figure 16-5. R/S Bit in First Byte .......................................................................................... 1007
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................. 1007
Figure 16-7. High-Speed Data Format .................................................................................. 1012
Figure 16-8. Master Single TRANSMIT ................................................................................ 1014
Figure 16-9. Master Single RECEIVE ................................................................................... 1015
Figure 16-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1016
Figure 16-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1017
Figure 16-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1018
Figure 16-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1019
Figure 16-14. Standard High Speed Mode Master Transmit ..................................................... 1020
Figure 16-15. Slave Command Sequence .............................................................................. 1021
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June 12, 2014
Texas Instruments-Production Data