TMS320C6655 Datasheet, PDF (140/232 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6655/57
Fixed and Floating-Point Digital Signal Processor
SPRS814—March 2012
7.6 DD3 PLL
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The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.
DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 65. For the best performance, TI recommends that all the PLL
external components be on a single side of the board without jumpers, switches, or components other than those
shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external
components (C1, C2, and the EMI Filter).
Figure 7-21 shows the DDR3 PLL.
Figure 7-21 DDR3 PLL Block Diagram
DDR3 PLL
DDRCLK(N|P)
PLLD xPLLM /2
BYPASS
0
PLLOUT
DDR3
PHY
1
7.6.1 DDR3 PLL Control Register
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can
be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs
exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence using
KICK0/KICK1 registers. For suggested configurable values see section 3.3.4 ‘‘Kicker Mechanism (KICK0 and
KICK1) Register’’ on page 72 for the address location of the registers and locking and unlocking sequences for
accessing the registers. This register is reset on POR only
.
Figure 7-22
DDR3 PLL Control Register 0 (DDR3PLLCTL0) ⁽¹⁾
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
BYPASS
Reserved
PLLM
PLLD
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
RW,+000000
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
Table 7-27 DDR3 PLL Control Register 0 Field Descriptions (Part 1 of 2)
Bit
Field
31-24 BWADJ[7:0]
23
BYPASS
22-19 Reserved
Description
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] if PLLM has even values or to be rounded half down of
PLLM[12:0] if PLLM has odd values. Example: PLLM=15, then BWADJ=7
Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
Reserved
140 Peripheral Information and Electrical Specifications
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