TCA9546A Datasheet, PDF (14/31 Pages) Texas Instruments – Low Voltage 4-Channel I2C and SMBus Switch with Reset Function

TCA9546A
SCPS205A – APRIL 2014 – REVISED FEBRUARY 2015
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9.6 Control Register
9.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9546A is shown in Figure 13. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
1 1 1 0 A2 A1 A0 R/W
Fixed
Hardware
Selectable
Figure 13. TCA9546A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
9.6.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9546A,
which is stored in the control register (see Figure 14). If multiple bytes are received by the TCA9546A, it will save
the last byte received. This register can be written and read via the I²C bus.
Channel Selection Bits
(Read/Write)
76 5
4
32
10
X X X X B3 B2 B1 B0
Figure 14. Control Register
Channel 0
Channel 1
Channel 2
Channel 3
9.6.3 Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). This register is written after the TCA9546A has been addressed. The four LSBs of the control byte are
used to determine which channel or channels are to be selected. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I²C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur right after the acknowledge cycle.
14
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