TCA9546A Datasheet, PDF (11/31 Pages) Texas Instruments – Low Voltage 4-Channel I2C and SMBus Switch with Reset Function

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TCA9546A
SCPS205A – APRIL 2014 – REVISED FEBRUARY 2015
9.3 Feature Description
The TCA9546A is a 4-channel, bidirectional translating switch for I²C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9546A features I²C control using a single 8-bit control register
in which the four least significant bits control the enabling and disabling of the 4 switch channels of I²C data flow.
Depending on the application, voltage translation of the I²C bus can also be achieved using the TCA9546A to
allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on
the I²C bus enters a fault state, the TCA9546A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.
9.4 Device Functional Modes
9.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of t_WL, the TCA9546A resets its registers and I²C state machine and deselects all
channels. The RESET input must be connected to V_CC through a pull-up resistor.
9.4.2 Power-On Reset
When power is applied to V_CC, an internal power-on reset holds the TCA9546A in a reset condition until V_CC has
reached V_POR. At this point, the reset condition is released, and the TCA9546A registers and I²C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V_CC must
be lowered below V _POR to reset the device.
9.5 Programming
9.5.1 I²C Interface
The I²C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 7).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 7. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 8).
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