LMH6702 Datasheet, PDF (14/25 Pages) National Semiconductor (TI) – Ultra Low Distortion, Wideband Op Amp

LMH6702
SNOSA03H – NOVEMBER 2002 – REVISED MAY 2016
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Typical Application (continued)
8.2.2 Design Requirements
The exceptional performance and uniquely targeted superior technical specifications of the LMH6702 make it a
natural choice for high speed data acquisition applications as a front end amplifier driving the input of a high
performance ADC. Of these specifications, the following can be discussed in more detail:
1. A bandwidth of 1.7 GHz and relative insensitivity of bandwidth to closed loop gain (characteristic of Current
Feedback architecture when compared to the traditional voltage feedback architecture) as shown in Figure 1.
2. Ultra-low distortion approaching -87 dBc at the lower frequencies and exceptional noise performance (see
Figure 9 and Figure 17).
3. Fast settling in less than 20 ns (see Figure 27).
As the input of an ADC could be capacitive in nature and could also alternate in capacitance value during a
typical acquisition cycle, the driver amplifier (LMH6702 in this case) should be designed so that it avoids
instability, peaking, or other undesirable artifacts.
For Capacitive Load Drive, see Figure 26, which shows a typical application using the LMH6702 to drive an
ADC.
ADC
+
R_S
LMH6702
-
C_IN
Figure 26. Input Amplifier to ADC
8.2.3 Detailed Design Procedure
The series resistor, R_S, between the amplifier output and the ADC input is critical to achieving best system
performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels
of ringing in the pulse response. Figure 27 in Application Curve (R_S and Settling Time vs C_L) is an excellent
starting point for selecting R_S. The value derived in that plot minimizes the step settling time into a fixed discrete
capacitive load with the output driving a very light resistive load (1 kΩ). Sensitivity to capacitive loading is greatly
reduced once the output is loaded more heavily. Therefore, for cases where the output is heavily loaded, R_S
value may be reduced. The exact value may best be determined experimentally for these cases.
In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly
loaded and some capacitance is present at the output. Due to the much higher frequency response of the
LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance
(parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this
susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be
minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high
frequency resistive loading.
Referring back to Figure 26, it must be noted that several additional constraints should be considered in driving
the capacitive input of an ADC. There is an option to increase R_S, band-limiting at the ADC input for either noise
or Nyquist band-limiting purposes. However, increasing R_S too much can induce an unacceptably large input
glitch due to switching transients coupling through from the convert signal. Also, C_IN is oftentimes a voltage
dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as R_S is
increased. Only slight adjustments up or down from the recommended R_S value should therefore be attempted in
optimizing system performance.
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