BQ24165_14 Datasheet, PDF (14/38 Pages) Texas Instruments – 2.5A, Dual-Input, Single Cell Switch Mode Li-Ion Battery Charger with Power Path Management

bq24165
bq24166
bq24167
SLUSAP4B – DECEMBER 2011 – REVISED MARCH 2013
DETAILED DESCRIPTION
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CHARGE MODE OPERATION
Charge Profile
Charging is done through the internal battery MOSFET. When the battery voltage is above 3.5V, the system
output (SYS) is connected to the battery to maximize the charging efficiency. There are 6 loops that influence the
charge current; constant current loop (CC), constant voltage loop (CV), input current loop, thermal regulation
loop, minimum system voltage loop (MINSYS) and input voltage dynamic power management loop (V_INDPM).
During the charging process, all six loops are enabled and the dominate one takes control. The bq24165/6/7
supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The minimum system
output feature regulates the system voltage to a minimum of V_SYS(REG), so that startup is enabled even for a
missing or deeply discharged battery. Figure 20 shows a typical charge profile including the minimum system
output voltage feature.
Regulation
voltage
Regulation
Current
VSYS
(3.6V)
Precharge
Phase
Current Regulation
Phase
System Voltage
Voltage Regulation
Phase
VBATSHORT
Battery
Voltage
Termination
IBATSHORT
Charge Current
50mA Linear Charge
to Close Pack
Protector
Linear Charge
to Maintain
Minimum
System
Voltage
Battery FET is ON
Battery
FET
is OFF
Figure 20. Typical Charging Profile of bq24165/6/7
PWM CONTROLLER IN CHARGE MODE
The bq24165/6/7 provides an integrated, fixed 1.5 MHz frequency voltage-mode converter to power the system
and supply the charge current. The voltage loop is internally compensated and provides enough phase margin
for stable operation, allowing the use of small ceramic capacitors with very low ESR.
The bq24165/6/7 input scheme prevents battery discharge when the supply voltages is lower than VBAT and
also isolates the two inputs from each other. The high-side N-MOSFET (Q1/Q2) switches to control the power
delivered to the output. The DRV LDO supplies the gate drive for the internal MOSFETs. The high side FETs are
supplied through a boot strap circuit with external boot-strap capacitor is used to boost up the gate drive voltage
for Q1/Q2.
Both inputs are protected by a cycle-by-cycle current limit that is sensed through the internal MOSFETs for Q1
and Q2. The threshold for the current limit is set to a nominal 5-A peak current. The inputs also utilize an input
current limit that limits the current from the power source.
14
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