ADS8410 Datasheet, PDF (14/40 Pages) Texas Instruments – 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER

ADS8410
SLAS493A – OCTOBER 2005 – REVISED MAY 2013
www.ti.com
The next two rising edges of CLK_O are shown as 17R and 18R in Figure 7. On 17R the LSB is latched out, and
on 18R SDO and SYNC_O go to 3-state. Note that BUS_BUSY falls t_d15 ns before the rising edge of SYNC_O
when MODE C/D = 0. Care must be taken not to allow LVDS bus usage by any other device until the end of the
read cycle or (t_d15 + 2/f_clk + t_d16) ns after the falling edge of BUS_BUSY.
DATA READ CYCLE END (With MODE C/D = 1)
A data read cycle ends after all 16 bits have been serially latched out. Figure 8 shows the timing of the falling
edge of BUS_BUSY and the rising edge of SYNCO with respect to SDO. SYNC_O rises on the 16th rising edge
of CLK_O. As shown in Figure 5 and Figure 6, the MSB is shifted out on the 2nd rising edge of CLK_O.
Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O.
CONVST
CS = 0
BUS_BUSY
t_d17
SYNC_O
CLK_O
SDO
15R 16R
17R
18R
t_d16
LSB − 1 _LSB
Figure 8. Data Read Cycle End with MODE C/D = 1
The next two rising edges of CLK_O are shown as 17R and 18R in Figure 8. On 17R the LSB is latched out and
on 18R SDO and SYNC_O go to 3-state. In cascade mode (with MODE C/D = 1), unlike daisy chain mode, the
falling edge of BUS_BUSY occurs after the LVDS outputs are 3-stated. One can use the falling edge of
BUS_BUSY to allow LVDS bus usage by any other device.
RESTRICTIONS ON READ CYCLE START
CONVST
t_d23
t_d24
BUSY
Read cycle not allowed
to start in this region
Figure 9. Read Cycle Restriction Region
The start of a data read cycle is not allowed in the region bound by t_d23 and t_d24. Previous conversion results are
available for a data read cycle start before this region, and current conversion results are available for a read
cycle start after this region.
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