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| ADS8410 Datasheet, PDF (13/40 Pages) Texas Instruments – 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER | |||
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www.ti.com
Conversion Phase
A
td19
RD_REQ (Int)
td11
BUSY
td10
BUS_BUSY O/P
CLK_O
td12
SYNC_O
SDO_O
ADS8410
SLAS493A â OCTOBER 2005 â REVISED MAY 2013
Conversion End
td4
0R 1F 1R
2R
3R
td14
MSB MSB â 1
Figure 6. Start of Data Read Cycle with End of Conversion
DATA READ CYCLE END (With MODE C/D = 0)
A data read cycle ends after all 16 bits have been serially latched out. Figure 7 shows the timing of the falling
edge of BUS_BUSY and the rising edge of SYNC_O with respect to SDO. SYNC_O rises on the 16th rising edge
of CLK_O. As shown in Figure 5 and Figure 6, the MSB is shifted out on the 2nd rising edge of CLK_O.
Therefore, the LSB-1 is shifted out on the 16th rising edge of CLK_O.
CONVST
CS = 0
BUS_BUSY
td15
SYNC_O
CLK_O
SDO
15R 16R
17R
18R
td16
LSB â 1 LSB
Figure 7. Data Read Cycle End with MODE C/D = 0
Copyright © 2005â2013, Texas Instruments Incorporated
Product Folder Links: ADS8410
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