ADS8410 Datasheet, PDF (11/40 Pages) Texas Instruments – 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER

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RD
SYNC_O
CLK_O
1F 1R
SDO
BUS BUSY
See Figures 5 and 6
See Figures 7 and 8
2R
D15
D14
ADS8410
SLAS493A – OCTOBER 2005 – REVISED MAY 2013
18F 18R
D0
Figure 3. Data Read With CS Low and BYTE = 0
As shown in Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is
in a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets
BUS_BUSY high at the start of the read cycle. The SYNC_O cycle is 16 clocks wide (rising edge to rising edge)
if BYTE i/p is held low and can be used to synchronize a data frame. The clock count begins with the first CLK_O
falling edge after a SYNC_O rising edge. The MSB is latched out on the second rising edge (2R) and each
subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling
edges of the clock. The next rising edge of SYNC_O coincides with the 16th rising edge of the clock. D0 is
latched out on the 17th rising edge of the clock. The receiver can latch the de-serialized 16-bit word on the 18th
rising edge (18R, or the second rising edge after a SYNC_O rising edge).
CS high during a data read 3-states SYNC_O and SDO. These signals remain in 3-state until the start of the
next data read cycle.
DATA READ IN BYTE MODE
Byte mode is selected by setting BYTE = 1; this mode is allowed for any condition listed in Table 2. Figure 4
shows a data read operation in byte mode.
RD
SYNC_O
CLK_O
1F 1R
2R
9F 9R
10R
18F 18R
SDO
BUS BUSY
D15
D14
D8 D7
D0
Figure 4. Data Read Timing Diagram with CS Low and BYTE = 1
Similar to Figure 3, a new data read cycle is initiated with the falling edge of RD, if CS is low and the device is in
a wait or sample phase. The device releases the LVDS o/p (SYNC_O, SDO) from 3-state and sets BUS_BUSY
high at the start of the read cycle. The SYNC_O cycle is 8 clocks wide (rising edge to rising edge) if BYTE i/p is
held high and can be used to synchronize a data frame. The clock count begins with the first falling edge of
CLK_O after the rising edge of SYNC_O. The MSB is latched out on the second rising edge (2R) and each
subsequent data bit is latched out on the rising edge of the clock. The receiver can shift data bits on the falling
edges of clock. The next rising edge of SYNC_O coincides with the 8th rising edge of the clock. D8 is latched out
on the 9th rising edge of the clock. The receiver can latch the de-serialized higher byte on the 10th rising edge
(10R, or second rising edge after a SYNC_O rising edge). The de-serialized lower byte can be latched on the
18th rising edge (18R).
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