TMS570LS0914_16 Datasheet, PDF (138/163 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS0914
SPNS225D – JUNE 2013 – REVISED NOVEMBER 2016
www.ti.com
Table 7-37. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)^(1)(2)(3)
NO.
1 t_c(SPC)M
2 ⁽⁵⁾
t_w(SPCH)M
t_w(SPCL)M
3 ⁽⁵⁾
t_w(SPCL)M
t_w(SPCH)M
4 ⁽⁵⁾
t_{v(SIMO-SPCH)M}
t_{v(SIMO-SPCL)M}
5 ⁽⁵⁾
t_{v(SPCH-SIMO)M}
t_{v(SPCL-SIMO)M}
6 ⁽⁵⁾
t_{su(SOMI-SPCH)M}
t_{su(SOMI-SPCL)M}
7 ⁽⁵⁾
t_{v(SPCH-SOMI)M}
t_{v(SPCL-SOMI)M}
8 ⁽⁶⁾ t_C2TDELAY
9 ⁽⁶⁾ t_T2CDELAY
PARAMETER
Cycle time, SPICLK ⁽⁴⁾
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low (clock
polarity = 1)
Pulse duration, SPICLK low (clock
polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
Valid time, SPICLK high after
SPISIMO data valid (clock polarity
= 0)
Valid time, SPICLK low after
SPISIMO data valid (clock polarity
= 1)
Valid time, SPISIMO data valid
after SPICLK high (clock polarity =
0)
Valid time, SPISIMO data valid
after SPICLK low (clock polarity =
1)
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid
after SPICLK high (clock polarity =
0)
Valid time, SPISOMI data valid
after SPICLK low (clock polarity =
1)
Setup time CS
active until SPICLK
high (clock polarity =
0)
CSHOLD =
0
CSHOLD =
1
Setup time CS
active until SPICLK
low (clock polarity =
1)
CSHOLD =
0
CSHOLD =
1
Hold time SPICLK low until CS
inactive (clock polarity = 0)
Hold time SPICLK high until CS
inactive (clock polarity = 1)
MIN
40
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – 6
0.5t_c(SPC)M – 6
MAX UNIT
256t_c(VCLK) ns
0.5t_c(SPC)M + 3
ns
0.5t_c(SPC)M + 3
0.5t_c(SPC)M + 3
ns
0.5t_c(SPC)M + 3
ns
0.5t_c(SPC)M – t_r(SPC) – 4
ns
0.5t_c(SPC)M – t_f(SPC) – 4
t_r(SPC)+ 2.2
ns
t_f(SPC)+ 2.2
10
ns
10
0.5*t_c(SPC)M + (C2TDELAY+2) *
t_c(VCLK) -
t_f(SPICS) + t_r(SPC) – 7
0.5*t_c(SPC)M + (C2TDELAY+3) *
t_c(VCLK) -
t_f(SPICS) + t_r(SPC) – 7
0.5*t_c(SPC)M + (C2TDELAY+2) *
t_c(VCLK) -
t_f(SPICS) + t_f(SPC) – 7
0.5*t_c(SPC)M + (C2TDELAY+3) *
t_c(VCLK) -
t_f(SPICS) + t_f(SPC) – 7
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_f(SPC) +
t_r(SPICS) - 7
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_r(SPC) +
t_r(SPICS) - 7
0.5*t_c(SPC)M + (C2TDELAY+2) *
t_c(VCLK) -
t_f(SPICS) + t_r(SPC) + 5.5
0.5*t_c(SPC)M + (C2TDELAY+3) *
t_c(VCLK) -
t_f(SPICS) + t_r(SPC) + 5.5 _ns
0.5*t_c(SPC)M + (C2TDELAY+2) *
t_c(VCLK) -
t_f(SPICS) + t_f(SPC) + 5.5
0.5*t_c(SPC)M + (C2TDELAY+3) *
t_c(VCLK) -
t_f(SPICS) + t_f(SPC) + 5.5
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_f(SPC) +
t_r(SPICS) + 11 _ns
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_r(SPC) +
t_r(SPICS) + 11
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t_c(VCLK) = interface clock cycle time = 1 / f_(VCLK)
(3) For rise and fall timings, see Table 7-2.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M ≥ (PS +1)t_c(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.
138 Peripheral Information and Electrical Specifications
Copyright © 2013–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS570LS0914