TMS570LS0914_16 Datasheet, PDF (103/163 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS0914
SPNS225D – JUNE 2013 – REVISED NOVEMBER 2016
eCAPx
(x = 1 through 6)
double
sync
6 VCLK4
Cycles Filter
ECAPx
(x = 1, 2, 3, 4, 5, or 6)
Figure 7-7. eCAPx Input Synchronization Selection Detail
7.3.1 Clock Enable Control for eCAPx Modules
Each of the eCAPx modules have a clock enable (ECAPxENCLK). These signals must be generated from
a device-level control register. When SYS_nRST is active-low, the clock enables are ignored and the
ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the
state of clock enable is respected.
eCAP MODULE INSTANCE
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
Table 7-11. eCAPx Clock Enable Control
CONTROL REGISTER TO
ENABLE CLOCK
PINMMR39[0]
PINMMR39[8]
PINMMR39[16]
PINMMR39[24]
PINMMR40[0]
PINMMR40[8]
DEFAULT VALUE
1
1
1
1
1
1
The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that
the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose
to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register
bit.
7.3.2 PWM Output Capability of eCAPx
When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM
output. This is called the Auxiliary PWM (APWM) mode of operation of the eCAPx modules. For more
information, see the eCAP module chapter of the device-specific TRM.
7.3.3 Input Connection to eCAPx Modules
The input connection to each of the eCAPx modules can be selected between a double-VCLK4-
synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12.
Table 7-12. Device-Level Input Connection to eCAPx Modules
INPUT SIGNAL
CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO eCAPx
eCAP1
PINMMR43[2:0] = 001
eCAP2
PINMMR43[10:8] = 001
eCAP3
PINMMR43[18:16] = 001
eCAP4
PINMMR43[26:24] = 001
eCAP5
PINMMR44[2:0] = 001
eCAP6
PINMMR44[10:8] = 001
(1) The filter width is 6 VCLK4 cycles.
CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO eCAPx⁽¹⁾
PINMMR43[2:0] = 010
PINMMR43[10:8] = 010
PINMMR43[18:16] = 010
PINMMR43[26:24] = 010
PINMMR44[2:0] = 010
PINMMR44[10:8] = 010
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Peripheral Information and Electrical Specifications 103
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