TM4C1232H6PM Datasheet, PDF (134/1172 Pages) Texas Instruments – Tiva Microcontroller

Cortex-M4 Peripherals
Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190
Note: This register can only be accessed from privileged mode.
The DIS4 register disables interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to
Interrupt 138. See Table 2-9 on page 93 for interrupt assignments.
Interrupt 128-138 Clear Enable (DIS4)
Base 0xE000.E000
Offset 0x190
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INT
Type RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10:0
Name
reserved
INT
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0x0
Interrupt Disable
Value Description
0 On a read, indicates the interrupt is disabled.
On a write, no effect.
1 On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN4
register, disabling interrupt [n].
134
June 12, 2014
Texas Instruments-Production Data