TMS570LS3137-EP_15 Datasheet, PDF (132/157 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

TMS570LS3137-EP
SPNS230D – OCTOBER 2013 – REVISED FEBRUARY 2015
www.ti.com
7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-24. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)^(1)(2)(3)
NO.
1 t_c(SPC)M
2 ⁽⁵⁾ t_w(SPCH)M
t_w(SPCL)M
3 ⁽⁵⁾ t_w(SPCL)M
t_w(SPCH)M
4 ⁽⁵⁾
t_d(SPCH-
SIMO)M
t_d(SPCL-
SIMO)M
5 ⁽⁵⁾
t_v(SPCL-
SIMO)M
t_v(SPCH-
SIMO)M
6 ⁽⁵⁾
7 ⁽⁵⁾
t_su(SOMI-
SPCL)M
t_su(SOMI-
SPCH)M
t_h(SPCL-
SOMI)M
t_h(SPCH-
SOMI)M
8 ⁽⁶⁾ t_C2TDELAY
Cycle time, SPICLK⁽⁴⁾
Pulse duration, SPICLK high
(clock polarity = 0)
–40°C to 125°C
Pulse duration, SPICLK low
(clock polarity = 1)
–40°C to 125°C
Pulse duration, SPICLK low
(clock polarity = 0)
–40°C to 125°C
Pulse duration, SPICLK high
(clock polarity = 1)
–40°C to 125°C
Delay time, SPISIMO valid
before SPICLK low (clock
polarity = 0)
Delay time, SPISIMO valid
before SPICLK high (clock
polarity = 1)
Valid time, SPISIMO data valid
after SPICLK low (clock polarity
= 0)
Valid time, SPISIMO data valid
after SPICLK high (clock polarity
= 1)
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
Hold time, SPISOMI data valid
after SPICLK low (clock polarity
= 0)
Hold time, SPISOMI data valid
after SPICLK high (clock polarity
= 1)
Setup time CS
active until SPICLK
high (clock polarity
= 0)
CSHOLD =
0
CSHOLD =
1
Setup time CS
active until SPICLK
low (clock polarity
= 1)
CSHOLD =
0
CSHOLD =
1
MIN
40
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – 6
0.5t_c(SPC)M – 6
0.5t_c(SPC)M – t_f(SPC) – 4
0.5t_c(SPC)M – t_r(SPC) – 4
t_f(SPC) + 2.2
t_r(SPC) + 2.2
10
MAX UNIT
256t_c(VCLK) ns
0.5t_c(SPC)M + 3 ns
0.5t_c(SPC)M + 3
0.5t_c(SPC)M + 3 ns
0.5t_c(SPC)M + 3
ns
ns
ns
ns
10
C2TDELAY*t_c(VCLK) + (C2TDELAY+2) * t_c(VCLK) - ns
2*t_c(VCLK) - t_f(SPICS) +
t_f(SPICS) + t_r(SPC) + 5.5
t_r(SPC) – 7
C2TDELAY*t_c(VCLK) + (C2TDELAY+3) * t_c(VCLK) -
3*t_c(VCLK) - t_f(SPICS) +
t_f(SPICS) + t_r(SPC) + 5.5
t_r(SPC) – 7
C2TDELAY*t_c(VCLK) + (C2TDELAY+2) * t_c(VCLK) - ns
2*t_c(VCLK) - t_f(SPICS) +
t_f(SPICS) + t_f(SPC) + 5.5
t_f(SPC) – 7
C2TDELAY*t_c(VCLK) + (C2TDELAY+3) * t_c(VCLK) -
3*t_c(VCLK) - t_f(SPICS) +
t_f(SPICS) + t_f(SPC) + 5.5
t_f(SPC) – 7
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) t_c(VCLK) = interface clock cycle time = 1 / f_(VCLK)
(3) For rise and fall timings, see Table 5-6.
(4) When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M ≥ (PS +1) t_c(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
132 Peripheral Information
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