TMS570LS3137-EP_15 Datasheet, PDF (1/157 Pages) Texas Instruments – 16- and 32-Bit RISC Flash Microcontroller

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TMS570LS3137-EP
SPNS230D – OCTOBER 2013 – REVISED FEBRUARY 2015
TMS570LS3137-EP 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
1
• High-Performance Microcontroller for Safety-
Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM interfaces
– Built-In Self-Test for CPU and On-chip RAMs
– Error Signaling Module with Error Pin
– Voltage and Clock Monitoring
• ARM^® Cortex™ – R4F 32-Bit RISC CPU
– Efficient 1.66 DMIPS/MHz with 8-Stage Pipeline
– FPU with Single- and Double-Precision
– 12-Region Memory Protection Unit
– Open Architecture with Third-Party Support
• Operating Conditions
– Up to 180-MHz System Clock
– Core Supply Voltage (VCC): 1.2 V Nominal
– I/O Supply Voltage (VCCIO): 3.3 V Nominal
– ADC Supply Voltage (V_CCAD): 3.0 to 5.25 V
– IP Modules GBD for -40°C to 125°C Only
includes Flash, MibADC timings, nPORRST,
N2HET, and FlexRay
• Integrated Memory
– 3MB of Program Flash With ECC
– 256KB of RAM With ECC
– 64KB of Flash With ECC for Emulated
EEPROM
• 16-Bit External Memory Interface
• Common Platform Architecture
– Consistent Memory Map Across Family
– Real-Time Interrupt Timer (RTI) OS Timer
– 96-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity Protection for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked-Loop
(FMPLL) with Built-In Slip Detector
• Separate Nonmodulating PLL
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• JTAG Security Module
• Trace and Calibration Capabilities
– Embedded Trace Macrocell (ETM-R4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– Parameter Overlay Module (POM)
• Multiple Communication Interfaces
– 10/100 Mbps Ethernet MAC (EMAC)
• IEEE 802.3 Compliant (3.3-V I/O only)
• Supports MII, RMII and MDIO
– FlexRay Controller with Two Channels
• 8 KB message RAM with Parity Protection
• Dedicated Transfer Unit (FTU)
– Three CAN Controllers (DCANs)
• 64 Mailboxes, Each with Parity Protection
• Compliant to CAN Protocol Version 2.0B
– Local Interconnect Network (LIN) Interface
Controller
• Compliant to LIN Protocol Version 2.1
• Can be Configured as a Second SCI
– Standard Serial Communication Interface (SCI)
– Inter-Integrated Circuit (I²C)
– Three Multibuffered Serial Peripheral Interfaces
(MibSPIs)
• 128 Words with Parity Protection Each
– Two Standard Serial Peripheral Interfaces
(SPIs)
• Two High-End Timer Modules (N2HETs)
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 160-Word Instruction RAM with Parity Protection
Each
– Each N2HET Includes Hardware Angle
Generator
– Dedicated Transfer Unit with MPU for Each
N2HET (HTU)
• Two 10- or 12-bit Multibuffered ADC Modules
– ADC1: 24 Channels
– ADC2: 16 Channels Shared with ADC1
– 64 Result Buffers with Parity Protection Each
• Sixteen General-Purpose Input/Output Pins (GPIO)
Capable of Generating Interrupts
• Package
– 337-Ball Grid Array (SnPb) (GWT)
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.