TMS320C5517_16 Datasheet, PDF (13/197 Pages) Texas Instruments – TMS320C5517 Fixed-Point Digital Signal Processor

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TMS320C5517
SPRS727C – AUGUST 2012 – REVISED APRIL 2014
4.2.3 RESET, Interrupts, and JTAG
Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions
SIGNAL
NAME
NO.
TYPE ^{(1) (2)} OTHER ^{(3) (4)}
DESCRIPTION
RESET
External Flag Output. XF is used for signaling other processors in
multiprocessor configurations or XF can be used as a fast general-
purpose output pin.
XF is set high by the BSET XF instruction and XF is set low by the
BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For
IPU
more information on the ST1_55 register, see the C55x 3.0 CPU
XF
M8
O/Z
DV_{DDIO Reference Guide [literature number: SWPU073].}
BH
For the XF pin's states after reset, see Figure 5-9, BootMode Latching.
XF pin can manually configured as Hi-Z state only in boundary-scan
mode. When this pin is in Hi-Z state, the IPU is enabled.
RESET
The IPU on this pin is disabled at reset.
Device reset. RESET causes the DSP to terminate execution and loads
the program counter with the contents of the reset vector. When
RESET is brought to a high level, the reset vector in ROM at FFFF00h
forces the program execution to branch to the location of the on-chip
IPU
ROM bootloader.
D6
I
DV_DDIO
BH
RESET affects the various registers and status bits.
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h).
The IPU is disabled at reset.
JTAG
For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference [literature number:
SPRU589].
IEEE standard 1149.1 test mode select. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
TMS
If the emulation header is located greater than 6 inches from the
device, TMS must be buffered. In this case, the input buffer for TMS
needs a pullup resistor connected to DV_DDIO to hold the signal at a
IPU
known value when the emulator is not connected. A resistor value of
L8
I
DV_{DDIO 4.7 kΩ or greater is suggested. For board design guidelines related to}
BH
the emulation header, see the XDS560 Emulator Technical Reference
[literature number: SPRU589].
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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Terminal Configuration and Functions
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